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Parallella Community • View topic - FPGA and Linux build environment for Parallella

FPGA and Linux build environment for Parallella

A forum for documenting the Parallella and Epiphany . (Not Q&A!)

FPGA and Linux build environment for Parallella

Postby peteasa » Tue Sep 01, 2015 8:06 pm

Hi all,

I just wanted to make you aware that build environment that I have published on Github now has a Getting Started guide at

The environment has a working FPGA bitstream with elink redesign and HDMI connection plus the necessary kernel and linux environment.

Enjoy!

Peter.
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Re: FPGA and Linux build environment for Parallella

Postby tif » Fri Oct 16, 2015 3:56 am

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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Fri Oct 16, 2015 3:13 pm

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Re: FPGA and Linux build environment for Parallella

Postby tif » Tue Oct 20, 2015 4:54 am

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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Tue Oct 20, 2015 8:07 pm

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Re: FPGA and Linux build environment for Parallella

Postby tif » Wed Oct 21, 2015 7:10 am

Generate output products produced the error
[BD 41-703] Peripheral </elink2/esaxi_0/S00_AXI/S00_AXI_mem> is mapped into master segment </processing_system7_0/Data/SEG_esaxi_0_S00_AXI_mem>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.

In the top of the Diagram window appeared a "Designer Assistance available. Run connection automation". It offers to connect two signals: axi_protocol_converter_0/M_AXI and HDMI0/M00_AXI.
I tried it and reverted it because it did not help.

So I opened the 7010_hdmi.xpr on the Win7 VM and reorganised the 7020_hdmi to have all blocks in the same place. The differences are:
HDMI_INT not connected to xlconcat_0
xlconcat has only In0 and In1 instead of In0 to In15.
xlconcat dout is not connected to processing_system7_0, which features no port IRQ_F2P.
There are a lot more missing links, apparently because processing_system7_0 has only 6 busses instead of 27.

I customized the processing_system7_0 IP to get all the required interfaces and connected them by hand. Now I would have to check all the customisation options which are not the same...
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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Wed Oct 21, 2015 7:06 pm

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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Sat Nov 21, 2015 6:05 pm

I know its a bit late but I have just found a fault in the 7010 build script. Xilinx insist on using full path names in the generated files. I tend to try to remove as many of these as possible and whilst doing other work I spotted that I had missed a full path to a file that would not exist on any machine apart from my machine. So I have now fixed that.
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Re: FPGA and Linux build environment for Parallella

Postby Kalicutt » Tue Dec 15, 2015 6:34 pm

Your guide has been a huge help to me getting started developing for my own custom application of the Parallella, which requires modification of FPGA, devicetree, Linux kernel, and software run on the device.

I have a few questions after having worked with the guide for a while:
1) I would like to base my work off of the current HDMI Embedded version of the image on the parallella website quickstart guide. This has the root file system, bitstream, devicetree, and kernel all separately compiled and working with the Parallella. It is possible to take a custom bitstream, created through customizing your Vivado HDMI project, and add it directly to the SD card's boot partition. However, in my case I also need to modify the device tree and linux kernel to add support for new devices. Changing the bitstream works fine, changing the device tree works fine, but when it comes to changing the kernel, I am not able to create a bootable image (or at least the Ethernet is not working not allowing me to access the device, since the HDMI never works). I notice you mention you are using the analogdeviceinc linux kernel version 3.19 branch 2015_R1. Is it possible to either directly or from within the yocto system provide the configuration used for the kernel? I have tried some of the default zynq configs, along with the parallella_defconfig in the parallella kernel repo, and nothing has worked so far.

2) Is it true that the headless version of the Parallella, without HDMI, does not have a stable Vivado project? I have seen evidence of this elsewhere but would like a direct confirmation.

3) The yocto building method is a lengthy process, is there a way to not have to remake the root file system? I am only interested in the device tree, bitstream, and kernel image.
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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Tue Dec 15, 2015 10:47 pm

The quick answer is yocto for everything or choose something else! If you just want to build the kernel why not build it on the parallella? There are posts about building the kernel on its own.. basically the process would be to get a working image with the matching kernel source, get the .config that was used to build the kernel from the environment then build the kernel source with that config and install that. Install that version of the kernel check it works then make your changes to the kernel driver source and rebuild. Have a look at viewtopic.php?f=48&t=1230 to start with. The trick would be to start with a distribution that has the matching kernel source.

I moved to the ADI kernel because I needed the hdmi drivers for the ADI fpga modules and it seemed to be easiest to patch in the couple of files needed to get the epiphany driver going than struggle to back port ADI kernel stuff to an older kernel. Since then I have been extending the epiphany driver and am using the latest oh fpga and it all still works quite well. Dont forget that yocto also gives you a full gui interface if you want so you dont just have to stick with the command line!

The headless Parallella does have a working Vivado project.. its in a zip file on the parallella-hw see https://github.com/parallella/parallell ... o/releases. What you have to do when mixing and matching is ensure that the get the correct matching epiphany sdk. That is what I try to present with my github parallella project.. the elink-redesign default branch uses the commit SRCREV = "be28d22caf3e09aa5813ec3a946279af2ee5191c" see https://github.com/peteasa/meta-epiphan ... dk_1.0.inc that works with this zip file! So you would build your kernel then build that version of the epiphany-sdk, build your fpga project based on that zip file and it would all work and you could use the epiphany chip.

Ok so if you must just build the bits that you need with yocto.. this is how I do it: bitbake -c cleansstate virtual/kernel will clean the kernel, bitbake hdmi-image-debug will build everything but if its already been built it will just build the kernel and put it in the deploy folder. Same thing with the device tree and the bitstream so bitbake -c cleansstate parallella-hdmi-bitstream and bitbake -c cleansstate device-tree will do what you want. Now you want to fix up the kernel and the device tree with your own bits.. create an bbappend recipe and override the SRCREV and the SRC_URI and you can pull in your own local git bare repository with whatever you want (SRC_URI = "git:///home/peter/Projects/parallella/parallella-hw-peter.git") for example... Or you can patch the kernel on the go... bitbake -c cleansstate virtual/kernel will clean the kernel, bitbake -c configure virtual/kernel will pull in the kernel and patch it.. then you can add your own patches then bitbake hdmi-image-debug to build. It does not build the rootfs because it does not know that you have done some manual patching. Anyway by the time it starts doing the rootfs the bits you want are already in the deploy folder so you dont even have to wait if the rootfs is being built you can just pick what you need and copy to the sd card. I still think that the neatest solution would be to build the kernel and the device tree on the parallella for what you want to do.. but anything is possible!
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