Random number generator with the FPGA

[shodruk]

[timpart]

Those figures for HDMI have confused me. If I'm reading the graph correctly the HDMI uses up a lot of Slice resource. So much so that the amount is more than than is available on the 7010 Zynq that was originally going to be used (and may still be for a cheaper option for non-Kickstarter buyers)

Is there unneeded HDMI logic being included accidentally? Or is it really the case that HDMI won't fit on the 7010?

Could someone explain where I'm getting this wrong please?

Thanks,

Tim

[shodruk]

someone needs HDMI sound, someone doesn't.
I don't know much about FPGA, but maybe HDMI with no sound (DVI-D) can be implemented on Zynq-7010.
Post KS version Parallella may possibly only support DVI-D due to cost, though it still can connect to TV with HDMI cable.
Because DVI-D signal is electrically compatible with an HDMI video signal.

Using HDMI transmitter chip is another choice, but there seems to be no space on the tiny credit card sized board.

[eleitl]

If I don't need HDMI (=bunch of headless node) and want to only do I/O (MPIlite in FPGA) is there enough space in a Zynq 7020 for that, to drive 6x8 FPGA I/O pins? The topology would be 6 links, with mini-Display port or mini-HDMI physical plugs. Would LVDS makes things more complicated or simpler?

Sorry if this is a repeat question, it does not generate a lot of interest, for some reason.

[aolofsson]

It "should" be fine, but it's going to depend entirely on the complexity of your design. The best way to explore if it fits is to download the free design tools from Xilinx and follow Roman's design guide for headless Parallella design:

http://www.adapteva.com/white-papers/pa ... nce-design

Andreas