Technical Details Epiphany-V

[stefanluik]

Hello,
could you tell some details about the chip ?
- Package size
- 16-bit external chip-addressing ?
- connection speed

Thanks
Stefan

[olajep]

[dobkeratops]

what would a ballpark "IO Clock Cycle" be, I understand you may want to clock it at different rates

is the potential bandwidth the same for GPIO and inter-chip links

[olajep]

[stefanluik]

thanks for replies,
I want just some secured infos:
- 1 billion processors are 1.000.000.000 processors. right ?
- what space is needed for the total chip ? what form factor (bga ...) is the total chip ?
- what will be the momentan thinking speed in GHz of the connection ports to neighbour chip ?

This infos are just for planning / designing a system like a supercomputer.

Thanks for

[sebraa]

I do not think you will get any secured infos. But I can speculate (since I am not with Adapteva and have never been).

A billion according to the US is 1.000.000.000.
Epiphany G3 and G4 chips are only available in BGA, so I would assume the same for G5. If they will be available to the public at all.
Given the 1024 GPIO signals specified, you can infer a reasonable package size.
The interconnect clock rate will be limited by the same physics that any other system has to deal with.

Do not expect miracles, only good engineering.