by timpart » Sat Jul 27, 2013 9:08 am
Architecture Reference Manual I'm looking at 4.13.01.14 The Adapteva website latest documentation has an out of date link to 3.12.12.18
In 4.2 I found parts of the discussion memory transaction ordering a bit confusing. Perhaps some examples with diagrams could be added after table 1 to make it clearer?
It says Load operations using data previously written use the updated values.
Does that mean written into a local register?
Table 1 says write to Core X followed by read from Core X is non deterministic. which contradicts this.
Also could you have a little table indicating which which instructions are Read and which are Write for the purposes of Table 1.
I presume LDR and TESTSET are Read and STR is write. The documentation for TESTSET is not clear on this point, but to my mind feels more like a Read with side effects.
I presume the reason that Read from X followed by Write to X is deterministic is that the core stalls until the Loaded data are returned? Otherwise the Write could easily overtake the Read if the loaded register wasn't referenced immediately.
EDIT: The Adapteva web site also calls version 4 of the SDK reference the latest, but I have 5.13.07.10 (from git hub)
Tim
