by greytery » Wed May 21, 2014 1:16 am
Thanks shodruck. Still struggling with the addressing concepts here .. - but having a lot of fun!
Tim - 'addressing memory on non-existent rows' .. Scary!
But what exactly do you mean?
And instead of moving to the left, what if we move to the right?
I'm not a HW/chip engineer- old ex-mainframe OS kernel hacker.
I don't understand how the FPGA is configured to map the E16 East-wards memory requests to the external DRAM, but it clearly does. There's some MMU magic/logic at the Zynq's Bank 35 interface to the E16.
OTOH, the FPGA also maps the ARM's memory requests onto the same DRAM - but represents that same physical space as different addresses for the host.
Seems that the memory can be as contiguous - or not - as the FPGA logic allows, or makes it appear to be. It's acting as a good old virtual paging kernel - like we had back in the good old '70s.
The FPGA provides the East eLink interface, then it must be aware of the Epiphany network routing protocol rules. For the default E16 placement of (32,8), then the FPGA may say : if the column number of an address request is less than 7, ship further East, else check row, etc. That gives a finite set of East and then North/South addresses. That is, along rows and then up/down columns that may have no physical cores on.
The further West/right we move the E16, there is larger FPGA virtual mapping space to the East because there are more columns. The potential for addresses sent to the FPGA interface by the E16 is limited to 4 rows (or they wouldn't get routed to the East interface), but the columns can be from 0 to 59. Similarly for the E64, but with 8 rows and 55 columns.
What would the addressing opportunities be if the E16 had coordinates of say, (32,60) to (35,63)?
(or some other position along the Western edge?)
Can the FPGA memory mapping really be this flexible?
The Parallella does not make use of the addressing to the West (a design choice somewhere), but that's effectively empty space.
tery
tery
