can you put a Forth compiler into each DSP core?

[timpart]

Not to mention the crap load of amazing games built for those 80's "home computers". The Sinclair ZX-81 had a flight simulator with 16KB memory! I dare to say that C64's "Raid over Moscow" required lot more resources than a Forth compiler.

Right, so who's going to write the FPGA HDL to wire up 16x joysticks and UHF modulators?

A lot of these games could have a second wind on mobile devices. No worries about RAM pack wobble interrupting your experience.

I have had a look at porting pForth (written in C). It compiles just fine and runs in emulation. The snags are the need for more than 32K of RAM and that the C compiler makes a meal of the inner interpreter loop, generating a lot of instructions.

Tim

[svartalf]

32 kBytes is tight, of course.

An alternative would be running an crosscompiler on one or two of the ARM cores.

32kB is tight? Heh...tell that to Chuck. He's doing it in less on his Green Arrays engines.

[svartalf]

I have a J1 VM running in ecore, right now don't have much functionality since I am still learning forth programming.
it is definitely possible to include the forth compiler.

Well done, that's great news! The J1 has simple instructions and does a lot of them. Will be interesting to see how fast it runs on actual hardware. I think the actual J1 has a relatively slow chip so Parallella might emulate about same speed.

Tim

In truth, why emulate? If the parallel cores are capable of stack based operation, you're probably better off implementing eForth or ColorForth by hand with a smallish amount of assembly code. (yeah, yeah, I know...)

As an aside, the J1 is only "slow" because it's implemented on a slow FPGA. It's fast enough to be a full-on co-processor for game dev for Arduinos by way of a really, really low-end Spartan 3.

[bithead]

32kB is tight? Heh...tell that to Chuck. He's doing it in less on his Green Arrays engines.

That's funny -- the day my Parallella arrived the post office also delivered my GA144A12 chip (with appropriate Schmartboard).

That day will be forever known as "The day I received 162 CPU cores in the mail."

I'm telling you, all of the interesting computing stuff is happening at the small level these days.

FWIW, I plan to throw a J1 onto the Zynq's fabric as soon as I can figure out how to do it without getting rid of the eLink stuff.

[timpart]

FWIW, I plan to throw a J1 onto the Zynq's fabric as soon as I can figure out how to do it without getting rid of the eLink stuff.

I look forward to hearing about your experiences. You 'll be using the ARMs as I/O processors?

TIm

[9600]

That's funny -- the day my Parallella arrived the post office also delivered my GA144A12 chip (with appropriate Schmartboard).

I had a play with one of those. Be interested to hear if you find an interesting application for it.

Cheers,

Andrew

[eleitl]

I love the sentiment that "32KB is tight".

The first computer we owned was a C64. There were a ton of compilers for it, including Forths.

Also, early versions of Turbo Pascal used 64KB for the editor *and* compiler.

Forth is a tiny language. Depending on the dialect you choose it can easily fit in 32KB including a compiler, editor and a bunch of code...

I come from a time where RAM was 1 k and clocks were in kHz. I've written code for systems which had just a few bytes (no k in front) of RAM and had a realtime OS with application bundled in 48 k ROM.

However, as a scientist I want to work with PByte data sets. And with 32 k/node every additional k used for the system is not available for the actual code.

[CIB]

I have a J1 VM running in ecore, right now don't have much functionality since I am still learning forth programming.
it is definitely possible to include the forth compiler.

I'd be interested in this for a project of mine. If you could share your progress on github or similar, it'd be highly appreciated.

[holder66]

I note with interest that the epiphany core has 64 registers. A few years ago, I programmed a neural network based pattern classifier in Power MacForth, a forth dialect that made use of the large number of registers in the PowerPC architecture to provide for passing named parameters (up to 8) to functions, which could be accessed as named local variables within the function, and of course made it child's play to call functions recursively. This not only made forth programming much easier since far fewer stack rearranging was necessary, it was also very fast. And the code was readable!

I hope that someone implements a forth machine on the parallela architecture. My pattern classifier would benefit greatly from running on multiple cores.

[ASterbini]

(from a recent Parallella owner)
While I was looking for a mips forth to put on the Epiphany cores
I found gForth (with metacompiler and cross compiler) and mips-forth,
a threaded forth implemented for the Spim simulator.

Has anybody tried to put gForth on Epiphany?