SDRAM / SRAM physical location and accesses

Any technical questions about the Epiphany chip and Parallella HW Platform.

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SDRAM / SRAM physical location and accesses

Postby kutoswiss » Mon Mar 05, 2018 9:53 pm

Hi everyone,

I'm a beginner about the Parallella board and I have few questions about it.

I have read that the Epiphany cores have access to 2 types of memory:
- The DRAM which a part of it is shared to all Epiphany cores (32 MB)
- The SRAM which is local for each Epiphany cores (32KB per cores)

My questions is:
Where are these memories are physically located on the parallela board ?
I guess the SRAM is inside of each eCore but how about the DRAM ?

Is it the SDRAM 1GB specified on page 10 of the parallella manuel reference ?
If yes, why do we only allocate 32MB as shared memory for all eCores ?

And also, all Epiphany cores can access this shared memory through the address 0x8f000000 (related to the linker fast.ldf).
How can it access to the shared memory with this address ? Is there an MMU or something between the Ephipany chip and the ARM ?

Sorry if my questions are a little bit newbie, but I need some brightening about this Parallella board :).

Many thanks in advance
Best,
ktsw
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Re: SDRAM / SRAM physical location and accesses

Postby jar » Tue Mar 06, 2018 3:11 pm

There's a slide with labelled ICs here:
http://www.adapteva.com/parallella-board/

Although there is 1GB of DRAM, only 32MB is shared between the ARM CPU host cores and the Epiphany cores. You can change this with some effort.

The 2D mesh network on chip (on Epiphany) handles the memory requests. Then there is FPGA interface glue that manages the off-chip memory access.
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