creating a output register/interrup from PL to arm processor

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

creating a output register/interrup from PL to arm processor

Postby dipin » Tue May 29, 2018 12:30 pm

hi,

finally i successfully implemented https://www.parallella.org/2016/01/21/creating-an-fpga-accelerator-in-15-minutes/ this project and added a counter. now output of the adder is printing in the Ubuntu terminal. Here i need an extra control signal or register to give some control to the total design. when the counter reaches a particular value, i need to give a signal to arm processor. so anybody know how to how to add and extra output reg to above design ?
any help is really appreciated
thanks and regards
dipin divakar
Last edited by dipin on Thu May 31, 2018 11:16 am, edited 1 time in total.
dipin
 
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Re: creating an extra output register from PL to arm process

Postby dipin » Wed May 30, 2018 12:16 pm

hi,
what i am trying to do is an interrupt which will goes from fpga to arm processor.. if anybody had any clue please help...
i can give it to the zynq processor by enabling the interrupt option. but how can i acess it in the arm processor
thanks in advance
dipin
 
Posts: 8
Joined: Tue May 08, 2018 10:47 am

Re: creating an extra output register from PL to arm process

Postby olajep » Fri Jun 08, 2018 2:26 pm

dipin wrote:hi,
what i am trying to do is an interrupt which will goes from fpga to arm processor.. if anybody had any clue please help...
i can give it to the zynq processor by enabling the interrupt option. but how can i acess it in the arm processor
thanks in advance


Check out the oh elink mailbox implementation:

Some pointers:

parallella_base verilog top block
https://github.com/parallella/oh/blob/m ... lla_base.v (search for mailbox_irq)

Vivado 'top block'
https://github.com/parallella/oh/blob/m ... d.tcl#L248 (search for mailbox_irq)

Device tree:
https://github.com/parallella/parallell ... 2677-L2678

Driver:
https://github.com/parallella/parallell ... 1.dtsi#L94

HTH
// Ola
_start = 266470723;
olajep
 
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Location: Sweden

Re: creating a output register/interrup from PL to arm proce

Postby dipin » Tue Jun 12, 2018 4:32 am

HI,

thanks for the replay olajep :)
i connected the my interrupt to zynq processor IRQ_F2P pin. and i am using this c program https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/scugic/examples/xscugic_example.c to get the interrupt working. but my problem is the xil_drivers .my drivers are throwing error .

now how can i get the interrupt in arm side of the parallella board . which drivers are required for it. Is it xilinx drivers or we need to write our on ??
did parallella will supply some interface for this?

please share your views
thanks and regards
dipin
 
Posts: 8
Joined: Tue May 08, 2018 10:47 am

Re: creating a output register/interrup from PL to arm proce

Postby olajep » Wed Jun 13, 2018 6:18 pm

dipin wrote:HI,

thanks for the replay olajep :)
i connected the my interrupt to zynq processor IRQ_F2P pin. and i am using this c program https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/scugic/examples/xscugic_example.c to get the interrupt working. but my problem is the xil_drivers .my drivers are throwing error .

IRQ_F2P is a 16 bit wide bus so you have to decide which pin you map it to.

See this xilinx forums thread:
https://forums.xilinx.com/t5/Embedded-L ... d-p/275370

dipin wrote:now how can i get the interrupt in arm side of the parallella board . which drivers are required for it. Is it xilinx drivers or we need to write our on ??
did parallella will supply some interface for this?
please share your views
thanks and regards


if you modify the device tree you should be able to use the uio_pdrv_genirq driver and then access your PL from user space.
This has been discussed previously on this forum search for "UIO"

// Ola
_start = 266470723;
olajep
 
Posts: 135
Joined: Mon Dec 17, 2012 3:24 am
Location: Sweden


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