Generate bitstream with Vivado 2019.x

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Generate bitstream with Vivado 2019.x

Postby mkaczanowski » Mon Feb 10, 2020 10:31 pm

Hey,
I am trying to generate bitstream with Vivado 2019.1 or 2019.2 but I am failing on the synthesis part.

Error:
Code: Select all
[DRC PLIDC-1] IDELAYCTRL missing from group with assigned IODELAYs: IODELAY cells have been found to be associated with IODELAY_GROUP 'IDELAY_GROUP', but there is no IDELAYCTRL associated with this IODELAY_GROUP.


Steps to repro:
Code: Select all
git clone https://github.com/aolofsson/oh
cd oh
curl https://gist.githubusercontent.com/mkaczanowski/908fed6fc00818d2715d2b11d71a8f83/raw/a811279614a39a462263afee61ba543e61bee58f/vivado.diff > /tmp/patch.diff
patch -p1 < /tmp/patch.diff
cd /home/admin/Projects/oh/src/parallella/fpga
make all


Did anyone succeed to built it or knows how to fix the issue?

Thanks,
Mateusz
mkaczanowski
 
Posts: 4
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Re: Generate bitstream with Vivado 2019.x

Postby olajep » Wed Feb 12, 2020 12:24 am

The fixes for that should be in my master branch here:
https://github.com/olajep/oh.git

That version is for Vivado 2018.2. You need to edit the block design scripts:
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23


The ADI IP's require Vivado 2018.2 so the HDMI bitstream builds will likely break.
You should be able to override that with "export ADI_IGNORE_VERSION_CHECK"

HTH,
Ola
_start = 266470723;
olajep
 
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Location: Sweden

Re: Generate bitstream with Vivado 2019.x

Postby mkaczanowski » Mon Feb 17, 2020 8:13 pm

Thanks a lot that helped. I tried with the older version 2018.2 and it works fine.
mkaczanowski
 
Posts: 4
Joined: Mon Feb 10, 2020 10:20 pm


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