Parallella Community

I wonder why the clock speed of E64G401 is limited to 800 MHz. Is this because of the latency of the FPU (fused multiply-add) inside each core or is it to preserve power?

Static power dissipation is a HUGE problem in advanced processes like 28nm, so the transistors are made quite slow. The main critical path was on chip SRAM access.
Best regards,
Andreas

We don't have a spreadsheet or "power simulator", but please look at the following video of the epiphany-IV. It shows the power consumption under different load conditions. (Including the code that ran).

https://www.youtube.com/watch?v=B9fpoJHUX0o

Thanks for the Information,
I was suprised that the SRAM access takes longer than the Floating point multiplier though.

That's because SRAM access needs to be single cycle and the floating point unit is spread out over 4 clock cycles.