Parallella Community

shouldn't it be 0.48ms transfer-time per core? also, I suspect there is some latency, a time where you cannot run any program because you're waiting for the data to arrive. would you calculate 16k per program, you probably could avoid that latency. as far as I know, there is no way to protect that local memory from local writes while making it accessible from dma-transfers.

to actually get 0.16ms transferrate for each 32k core, you would need to attach the fpga to the north and south eLink. and then you would need to program it...

finally, you should consider where data is sent when, so data isn't stalled because of other cores doing a transfer at the same time. especially if you actually get input from 3 connections...