Parallella Community

I wanted to present my idea for a kind of souped-up Parallella specification. I just found out about this board, so I haven't bought one to try to do a proof-of-concept program. I also doubt this model would be financially viable because of expense and it would have a rather small market. This is based on an architecture I ran into at work, so I am going be vague about some details. It still should be pretty easy to figure out what chips I am talking about though.

Essentially, it would use the Parallella++ as a digital back end for a wide-band intermediate frequency modem of sorts. I ran some numbers and it appears to be possible. It relies on quadrature down conversion in the receiver and a quadrature up conversion in the transmitter in order to minimize some of the processing and bandwidth requirements. The point of reference in terms of samples and bandwidth is 200 MSPS of each I and Q data in both directions, leading to a modulated bandwidth of 160 MHz in both directions. That would allow up to 800 Mbit/s with 1024QAM or 960 Mbit/s with 4096QAM of raw unidirectional bandwidth over a considerable distance. If I got the calculations right.

Interface to the transmitter and receiver in this system would be JESD204B, 2 lanes each direction, which is where the cost comes in. I am sure Xilinx would love to charge an arm and a leg for the JESD204B IP. In addition to the cost from tan upgrade to the pin compatible ZYNQ-7015 or ZYNQ-7030. The transmitter and receiver chips are actually reasonably priced, probably costing as much as the ZYNQ-7015 and Epiphany combined.

So we would have the following:
The Parallella++ with:
A 16 or 64 core epiphany, I am not sure exactly how much computing power would be needed at this point.
A ZYNQ-7015(speed grade 2) or 7030, depending on how much processing needs to be done in the fpga fabric. These have 4 high speed transceivers for the JESD204B.
Dual Gigabit Ethernet,
A JESD204B Compliant clock generator for synchronizing the whole shebang

The daughter board containing a trasmitter DAC and a reciever ADC.

The fpga would be good for resampling the transmitted and received signals, essentially interpolating and then decimating by integer values in order to match the signal to the sample rate. This would also allow us to minimize the bandwidth to the Epiphany co-processor, especially if we only use it for the receiver structure. Bandwidth required is dependent on if we are using the original 16 bit integers for our samples or we are using fp32 for the resampled signal. Either way it might be possible to get away with one eLink, though it would be safer to have 2. The zynq would have an extra fifty pins compared to the Z-7010 Parallella, or 25 more than the Z-7020 to allow this.

The Epiphany would essentially implement the final stage detector, compensating for phase drift and gain or telling the fpga how too. All while implementing a detector which would figure out what symbols were the most likely to have been sent, checking that against the error correction scheme, and finally translating the incoming symbols to a final bit-stream for the ARM cores to transmit over Ethernet.

So there you go, at most 500-1000 dollars in hardware costs, and way more than that for the required IP. All for something you probably can just plug into itself.

I have no hardware knowledge, so can you explain to me what's this good for?
googling told me JESD204B is just a serialized connection for up to 12Gbit/s.
I guess, the 3GBit/s mode could be used at max for interfacing with epiphany.
but what next? unless parallella++ can emulate the JESD204B IP I see no point.
or do you think of attaching sensors which deliver those 12Gbit/s of data?
other than that I see no reason why you need epiphany chip at all.
isn't the JESD204B IP doing all the work with calculations and stuff?
somehow google didn't show anything about any computing requirement...

JESD204B is a communication's interface. I was thinking that a zynq-7015 or 7030 possess 4 high speed transceivers at rates of up to 6 Gbit/s. The transceivers also possess serializer/desearailizer circuitry for interfacing to the rest of the system. Running 200 MSPS of I and Q data would only require two lanes in at 4 Gbit/s and 2 lanes out at 4 Gbit/s. The JESD204B interface is primarily for reducing the number of data lanes in and out of the converters. Also it is the interface on many new high speed converter's out today.

The computing requirements would be for processing the I and Q symbols coming in and out. They still have to be converted to bit streams. There is also no guarantee the conversion will go smoothly. The epiphany would provide some much needed computing backbone for the system. FPGA fabric could be used to implement some of the more fixed-function parts of the process.

so, what you write here is: except for the expensive zync, no further hardware is needed.
(well, of course the cable still would be expensive too.) you hope epiphany will do the protocol.
did I understand this correctly? so in the end you get a device for debugging JESD204B anywhere.
well, of course provided it uses a speed slower than 4Gb/s, since epiphany cannot talk faster, yet.

could you please give more details on what is needed?
maybe some links to the actual description of I and Q symbols?
why did you write more connections would be required, when JESD204B is reducing their number?
what hardware do you need in addition to the zync? any links on such success stories from diy community?

and did you have any particular device in mind with which your parallella++ could talk?
imho it is strange a new protocol appears, and it costs >2000$ to make use of it.
definitely wont make that protocol any more popular...
from what I read, you basically must fourier transform the analogue signal to calculate if hardware will work.
guess that's what the software-side does do, and I suspect that's where the high costs come in, for the software.
the users wont pay for that, since the sold device either works or doesn't work.
nobody but the developers really wants to know why it doesn't work...

Its kind of unclear, but each transceivers on the Zynq have both a receive and transmit line. Though they are in one block, so I am unsure how they would work connecting to multiple devices. That way you could have four outgoing lines and four incoming lines. Allowing for you to connect quite a complex system to a Z-7015 or Z-7030. It would make for quite the software defined radio platform.

Alternatively, working with current Parallella hardware, an Artix-7 35t or 50t can be had in a two or four transceiver package for less than a hundred dollars. Then you could connect to the two off board eLinks on the current Parallella to the Artix and route the data through the Epiphany. That gives you plenty of FPGA fabric and computational resources to work with in stages.

I still have the wonder what exactly are the cost/performance/power/size tradeoffs are for doing demodulation/modulation through an Epiphany vs. through an FPGA. Certainly the limiting factor for the Epiphany would be how much data you can cram through the eLink interface.