Parallella Community

Hi,

If you ever do an ISA revision, something that could help 'stream' processing is a pre-fetch instruction.

Basically, you just do a "fetch [addr]" and this is non-blocking, just issues a read request. When the result comes back, it's pushed in a small fifo (only need a few elements depth) and then you have another instruction to read from that fifo with ver low latency.

This would allow to hide external fetch latency without using the DMA. Sometimes you don't know addr "much" in advance and doing a DMA of like 16 words is a bit of a waste of time. When using the DMA for "large" chunks, you also need to dedicate space for a "ping-pong" buffer which makes you loose some precious space.

Just a thought for the future.

Cheers,

Sylvain

Another, more straightforward, idea would be to make loads non-blocking, that is simply claim the target register until the write returns, don't block the pipeline prematurely...
(might be a lot more difficult than it sounds, I am not all that familiar with circuit design)

Yeah, it would be more difficult to do in HW because you'd need a bunch of logic to keep track of register dependency.
While with a fetch you just issue a read on a address in the emesh with a return address being in the 'register' zone and that poins to some small hardware FIFO.