RAW and WAW hazard avoidance

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Re: RAW and WAW hazard avoidance

Postby ysapir » Thu Aug 08, 2013 5:03 pm

An instruction should execute as soon as it can. I don't see how stalling the AND for having dual issue with the FADD (or a similar combination) can help in accelerating any program? In this case there will be no dual issue.
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Re: RAW and WAW hazard avoidance

Postby Gravis » Thu Aug 08, 2013 9:09 pm

@ysapir
can you confirm if the proposed method is in fact who it's done on the epiphany chip? i really would like to get this right for the emulator.
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Re: RAW and WAW hazard avoidance

Postby timpart » Mon Jul 14, 2014 11:55 am

It seems from Notzed's experiments that a floating point instruction can delay a IALU instruction by dual issuing with it then discovering that the FP instruction's registers aren't ready. See , the part after the "Update" .

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Re: RAW and WAW hazard avoidance

Postby notzed » Thu Jul 17, 2014 1:29 pm

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