3D parallella?

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3D parallella?

Postby 8l » Thu Sep 19, 2013 4:23 pm

is 64 cores x 8 layers (512 cores)in parallella possible?

8 cores (x axis) * 8 cores (y axis) * 1 layer (z axis)
8 cores (x axis) * 8 cores (y axis) * 2 layers(z axis)
...
8 cores (x axis) * 8 cores (y axis) * 8 layers(z axis)

processor–processor and processor–memory communication
could be implemented in n-dimensional mesh.
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Re: 3D parallella?

Postby ysapir » Thu Sep 19, 2013 4:52 pm

Parallella Cube? :)

In terms of the address space, there is no reason why not - you utilize 1/8 of the available space. However, notice that the memory scheme is 2-D (i.e., "flat"), not really 3-D. So, the 3D-ness would come from your remapping of the 12-bit coreID, possibly into three 4-bit groups, and doing the coordinate space conversion in software.

As for the physical connection - if we can stack 4 parallellas in a cluster, why not 8?
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Re: 3D parallella?

Postby 8l » Thu Sep 19, 2013 11:49 pm

yes, current memory is 2d, but 3d memory will be available sooner or later.
look at my previous post.
http://hybridmemorycube.org/
viewtopic.php?f=10&t=246

TIA
--
brain is not "flat"
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Re: 3D parallella?

Postby ticso » Fri Sep 20, 2013 4:16 am

Different story.
HMC memory has physical 3D stacked dies in the same way it was asked for epiphany.
This is just a different physical position of the same technology to have shorter wiring and smaller boards.
Lock at a standard PC - flat cards are inserted side by side.
DIMMs are inserted side by side - basicly laying RAM dies on top of each other in different ICs on different boards with hughe air gap.
Some RAM DIMMs have piggy packed ICs getting smaller distance between dies.
Now there is piggy packing dies inside an IC.

the 2D scheme was about epiphany internal layout for core addressing.
This is 2D as there are 4 links between cores.
And this is not exactly memory as such - it is the internal mesh between these memory/core combos.
The resulting memory as seen from the outside has a scheme depending on the viewpoint.
One address = 1D.
Consider Address plus bits and you have 2D
Consider address splited in RAS CAS and you have 3D.
Consider additional bank and you have 4D.
In the end everything results in one flat 1D address space with one 8bit number at each location no matter how the physical bits are geometrically located.
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Re: 3D parallella?

Postby ticso » Fri Sep 20, 2013 4:18 am

PS:
Most parts of the brain is very flat.
It only has a few neuron layers.
It is just folded like a used piece of paper to fit inside a head.
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Re: 3D parallella?

Postby 8l » Wed Oct 23, 2013 12:01 pm

IBM unveils concept for a future brain-inspired 3D computer
http://www.kurzweilai.net/ibm-unveils-c ... d-computer
Image
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Re: 3D parallella?

Postby hewsmike » Thu Oct 24, 2013 1:09 am

Hmmm .... how 'flat' is the brain ?? That's a hard one indeed. Certainly the cortex ( surface, grey stuff, neuronal cell bodies ) is foliated and could be suitably mapped ( smoothly, say conformally ) to a plane but the key functionality lies in the interconnections. Most of the interior ( white stuff, axons ) is vast bundles of wiring that connect the cortical neurons to each other and to deeper ganglia, long motor and sensory tracts etc. How many dimensions you could legitimately map that to is anyone's guess : I'd say it's fractal, as nature seems to do that alot when there is tension between different optima ( eg. the respiratory and vascular 'trees' are trade-offs b/w limited volume and maximal surface area ).

Cheers, Mike.
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