Parallella Community

Andreas Olofsson mentioned in his keynote address (see Youtube) that %10 of the power consumption goes to interfacing and almost %90 goes to the FPU.
Is there are power cost breakdown structure available? I believe the floating point multiplier is responsible for the majority of the power consumption. (Its usually the multiplier in DSP chips).
If we avoid using the floating point instructions can we get further power savings?
This question is for the designers of the Epiphany.
Thanks in advance.

Yeah it'd be interesting to know which part is dynamic power and which part is static power.

Using 16bit width instructions may reduce power consumption, too.