Parallella Community

What does off-chip read/write and on-chip read/write mean? On-chip I can imagine that is read/write in the cores within the epiphany chip, right? But what is off-chip?

Thanks!

Hhm, a n00b question:
Does it need more time for the 4 "inner" cores to get code + data through the 12 "outer" core areas ?

*gasp*

Actually, it does, in some way. Data travel on the eMesh takes time - 1.5 cycles per hop, assuming no congestion. Assuming that the data gets to the cores from an eLink, which is connected at the edge of the chip, it takes longer to get to the center core, and even longer to get to the other side of the chip. However, this is *latency*, which affects only the arrival of the first transaction in a series. after that, following transaction arrive at the speed they enter the chip, so the throughput is maintained.

That said, typically, the latencies are much smaller than the processing time, so this should not really be a design consideration.

I guess it is (35, 11) (south east core).