Parallella Community

@vidarh
sorry, for some reason i thought you were talking about a router with deep packet inspection. a very derp moment.

anyway, do remember that a switch has to deal with network congestion and error detection. i would suggest one core for receiving data and one core for sending, if you can manage it, making 8 ports possible with the 16 core chips. assuming it works, i'm unsure of if/how you could scale this up to more cores. if you were unaware, you will need an FPGA to handle the I/O translation.

good luck.

ZYNQ-7030 has Gbps transceivers, but it seems very expensive.
PC is too complicated and blackboxed, so we need a lot of hardware/software/money resources only for communicating with PC.

Vidarh,
I think there are questions in multiple dimensions.
1) could it be done, possibly; probably not easily. However let's not forget the fundamental formulae of product management:

Anyfeature = f(time,$)
Time = f($)

2) should it be done? Unless it was built as a fairly high volume product, I don't think it would be less expensive than current products.

3) There are dedicated network computer SoC's like the Atheros 7161 that have the functions, sdks, and reference designs to handle over 75,000 1500B packets per second. They are inexpensive enough that they are found in commodity router/AP's. For some "unusual" proofs of concept, we've cracked open the covers of one, loaded an open source software stack, and have done all sorts of funky/fun stuff.

4) I don't recall the model numbers, but getting above 1Gbit, Freescale has a multicore network SoC with 10G or 4x2.5G, and a lot of network functions in silicon rather than software.

5) finally, bigger isn't always better. Very few commonly used computers can push 10G. Most can't push 1G through an application. I would be inclined to use 10G PHYs on the storage side connected to a layer2/3 high speed router, a fast mesh and a lot of 1G ports. If you really have enough of a beastly machine to push substantially more that 1G out, I would link-ag a 4-port PCI NIC.

None of the above is intended to suggest that a good network product could not be designed with Epiphany, particularly as the number of cores grows. However, I believe (sans much serious analysis) that it would require an Epiphany based custom board and custom system design as opposed to a set of Parallellas.

Now, if you have the time and resources, a potentially worthy contribution would be porting some of the open source router OS's to Parallella, not so much as an alternative to a high performance router, but to characterize where the non-parallelizable code is. That would be a step toward an epiphany accelerated high performance router using a board with more Epiphany, more cores, lots more DRAM, multiple FPGAs.

Meanwhile have a look at Bittware's use of Epiphany in the Anemone product. (http://www.bittware.com/products-servic ... -for-fpgas). I think that's closer in the near term to the type of IO processing architecture you'd want (coupled with a high performance network processor). Parallella is a great step forward in make dev kits for these kinds of systems accessible and affordable at the parallell software level. Many more people will be able to stretch the boundaries of what can be built because of it.