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It is not clear when the bit corresponding to an interrupt is cleared in the ILAT register. This should probably be added to Figure 15 in section 7.8.1, unless of course the assumption is that software will clear it? That would seem odd, though, as Epiphany's interrupt mechanism seems to be very similar to Blackfin's, which does clear it in hardware.

Good catch! The ILAT[N] bit is cleared automatically by the hardware at the same time that the PC jumps to the IVT entry and the previous PC is saved n the IRET.
Andreas

Good catch! The ILAT[N] bit is cleared automatically by the hardware at the same time that the PC jumps to the IVT entry and the previous PC is saved n the IRET.
Andreas

OK, thanks.

While I have you here: In Figure 15, one of the conditions for handling an interrupt is "~|IPEND[N:0]". I'm not sure I understand this. What's the "|"? And why the extra ":0"? Perhaps it's just meant to say "~IPEND[N]"?

This is the Verilog HDL convention. It means the logical inverse ("~") of the logical OR ("|") of all bits 0 to N of bus IPEND.

It gets set around the same time IRET gets set, it seems: https://github.com/adapteva/epiphany-cg ... .cpu#L1050

-Writing it out the description of IPEND in words as well:

-The IPEND records data about all ISRs that have started but have yet to finish (with an RTI instruction).

-The IPEND has the same number of bits as the ILAT register, with each bit position in the IPEND matching up to the
same bit number position in the ILAT register.

-If a new interrupt comes into the interrupt controller, before it can start, the interrupt controller checks the IPEND register
to see if there are any currently active interrupts (with the IPEND bit set) with equal or higher interrupt level. Bit zero is the
highest priority interrupt corresponding to the SYNC interrupt. The USER interrupt has the lowest priority.

-To illustrate the priority aspect, if a SYNC interrupt comes in and the there are other interrupts currently active, the SYNC ISR will still kick off (assuming the global interrupts are enabled and the IMASK bits aren't set)

..sorry for the long winded statements, hope they help more than confuse.

Andreas