Parallella Community

The architecture manual says that TESTSET is atomic, but how atomic is it? Is it only atomic with respect to other Epiphany cores, or is it atomic with respect to host cores, for instance? This is pretty significant when writing to external memory.

TESTSET instruction is only atomic when used together with the "epiphany memory" (the distributed chunks of 32KB per core) and does not work on memory outside the Epiphany chip (like DRAM) unless the atomic functionality is implemented within that memory.

Does it raise an exception of some kind if used on unsupported memory? Or what exactly happens?

Another thing for the manual. ;)

@aolofsson can you confirm that @over9000 is correct in assuming that normal memory accesses to invalid memory will result in undefined behavior?

Yes, for all practical purposes memory access to unmapped memory (read or write) will cause unpredictable behavior and most likely will cause the system to hang.

Two more questions:

1. How would I reset a core that's stuck reading unmapped memory? (This should probably be clarified in the manual too, where it just says that a core will most likely need to be reset.)
2. What happens if a core reads from the two reserved local memory banks? Undefined behavior? Or will it work, but just not be very future-proof? This should probably be documented (in some capacity) too.

1.) We will publish a recipe for resetting a core that is as safe as possible. One of our interns struggled with this task over the summer, it's not straightforward.

Not sure I understand what you mean by the two local reserved memory banks?

2.) The local memory from 0x00000000 to 0x000EFFFF is aliased so reading/writing to any location in this range will work. Address bits [19:15] are simply ignored in the access logic. Behavior should be defined, but code will not be future proof for chips with more memory. (although 19:16=1111 means an MMR access)

By reserved memory banks I mean local addresses 0x00008000 and 0x000F0800.