Parallella Community

Hi there,
I just placed order of Engineering sample chipset and I'm designing supercomputer based in Adapteva chipset 16 cores, but I have couples of questions:
After doing review in ep skd, I didnot found clear informations regarding the COLID and ROWID pins for chipset,
1) is this PIN as input I could use it to setup address ID of each chipset like doing address setup for I2C bus ?
2) I readed a article from adapteva that , designer could uses 64 chipset as max, if this true then as we know from datasheet we have 0x0 to 0xf for COLS , and the same for row, but wich the best matrix to use to link 64 chipset thru elink protocol ?
3) if 64 chipset could placed this mean 1024 cores, what the external memory capacitance should I interface in zynq7020 ?.
4) in PIN E12 it said DSP_FLAG, is this indicator used as FLAG to indicat CHIPSET is free, or for wich purpose ? if yes then I could I interface small FPGA to handle 64 bits in parallel and convert it in serial to be proceed by zynq7020 and this needs some minor changes in HAL libs ???

Best regards
Nizar