Parallella Community

The manual says that a software exception can be triggered when an invalid instruction is encountered. However, it does not specify what value should be written to EXCAUSE for this case (see the table in Appendix D).

Thanks for catching this,I added it to the opcode table. There is an undocumented "UNIMPL" instruction with an opcode as follows:
0xXXXFXXXF

The instruction works like a NOP, except for the fact that it causes a software exception (and flushing the pipeline).

Andreas

Does UNIMPL cover every possible illegal instruction bit pattern? I.e. can I try to match every other instruction in the ISA and simply fall back to UNIMPL if none match?

Relatedly, what should happen if an instruction decodes successfully but has nonsensical fields? For example, a MOV<BL> makes no sense.

Sorry, the unimpl is only one specific Opcode. Executing a non-supported opcode will result in weird and unpredictable behavior.

Andreas

OK. Table 24 in section 7.8.1 should probably be fixed to say "unimplemented exception" instead of "invalid instruction" then. It should probably also be documented that invalid instructions are undefined behavior.

Is it OK for a simulator to simply set ACTIVE=0 for these cases?

Yes, that sounds right.
Thanks.