Parallella Community

about zero-copy ring buffer, this blog seems provide enough introduction.

about my suggestion. what I mean is, adding another GE interface is not the point. First you need to have a chip that convert serial signal to parallel (serdes), be it from phy or from some FPGA with GT*. Even you get two GE, you IO bandwidth towards epiphany is not not enough. it only has 1.4Gbps, way below 2Gbps needed to transfer and receive GE traffic.

So focus on what are you gonna do with the current hardware to reach its potential.

btw, for the ephiphany chip, remember the speed to access DDR is 10 times slower than the 32K SRAM.

A few comments:

- you can have external phys (actually you must, even the GtP can't do Gb ethernet natively) and connect those to either a PL MAC or one of the two PS MAC (through RGMII or GMII). Then which ever MAC you choose, you can connect it to the internal AMBA interconnect and access it from the ARM.

- the epiphany bandwidth doesn't need to be a limitation. A high perf router would only look at the headers anyway, so there is no reason to send more than that to the epiphany, the rest of the data can say in internal buffer in BRAM or the on-chip SRAM, or the DDR. If you want to do super fancy deep packet inspections that needs to look at the payload or every single packet, you probably wouldn't do it at line rate anyway ...

- DDR access is 10x slower only when doing big move with the DMA. Random accesses are more like 150x slower.