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The TESTSET instruction has an S field in the decode table, like other LDR/STR instructions. What does it mean? the Operation description of the instruction does not mention any way that this bit might affect the instruction's semantics. Perhaps it's there by mistake?

Similarly, the B0-B1 bits don't make much sense as it's a purely word-sized operation.

There should be hardware support for TESTSET RD, [RN,+/-RM], but we limited it to TESTSET RD, [RN,RM] unless someone sees a pressing need for the subtract option?

It is up to the user(assembler) to generate the right bit pattern for B1 B0 (meaning 10). Any other value in combination with the TESTSET opcode will cause "undefined behavior". Sorry to keep coming back to that..

Oh, it's okay. I just think the manual should explicitly list the expected bits for this instruction in the decode table, then, since it's not like software has a choice as to what to encode/decode here. Same goes for the S bit (though I assume the S bit isn't considered at all?).

What do you mean regarding the subtract bit? Does this mean that presently, the instruction will just do RN+RM? I'm fine with either, but I think the TESTSET section in the manual should reflect that only addition works, then.

@aolofsson ping :)

What I meant to say is that the St bit "may" work with TESTSET, but we haven't tested it and it may not even be supported in the assembler. Let's just say that it doesn't work and I will make sure the manual/opcode table is updated to reflect this restriction.