Change Origin in HDF file

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Change Origin in HDF file

Postby msuthar25 » Tue Jul 29, 2014 9:09 am


I want to know if i can change the default origin of my epiphany III from (32,8) to (0,0) in the HDF file?
If not why?

Thank You
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Re: Change Origin in HDF file

Postby 9600 » Tue Jul 29, 2014 10:15 am

Please see the Parallella Reference Manual, pp. 23:

The Epiphany chip is situated within a 1GB section within the Zynq host processor memory
map. The offset within the 1GB space occupied by an Epiphany coprocessor is set by the
ROWID and COLID pins on the Epiphany chip. The ROWID and COLID can be individually
set on boards through the PEC_POWER connector enabling direct board to board connection
through the PEC_NORTH and PEC_SOUTH connectors. By default the address locations of the
Epiphany cores on Parallella-16 are as shown in the Table below.

Chip Core Number Start Address End Address Size
(32,8) 80800000 80807FFF 32KB
(32,9) 80900000 80907FFF 32KB
(32,10) 80A00000 80A07FFF 32KB
(32,11) 80B00000 80B07FFF 32KB
(33,8) 84800000 84807FFF 32KB
(33,9) 84900000 84907FFF 32KB
(33,10) 84A00000 84A07FFF 32KB
(33,11) 84B00000 84B07FFF 32KB
(34,8) 88800000 88807FFF 32KB
(34,9) 88900000 88907FFF 32KB
(34,10) 88A00000 88A07FFF 32KB
(34,11) 88B00000 88B07FFF 32KB
(35,8) 8C800000 8C807FFF 32KB
(35,9) 8C900000 8C907FFF 32KB
(35,10) 8CA00000 8CA07FFF 32KB
(35,11) 8CB00000 9CB07FFF 32KB

So you would also have to configure the Epiphany offset via the PEC_POWER connector.


Andrew Back (a.k.a. 9600 / carrierdetect)
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Re: Change Origin in HDF file

Postby aolofsson » Tue Jul 29, 2014 1:50 pm

There are too many interdependencies at the moment, so I wouldn't recommend it. For example, you would need to change the FPGA code and regenerate the bitstream. Also, (0,0) wouldn't work since this is used as a local alias for all cores. (ie number without an area code).
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