High speed data aquistion and storage

Any technical questions about the Epiphany chip and Parallella HW Platform.

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High speed data aquistion and storage

Postby sneuf0897 » Tue Aug 05, 2014 9:07 pm

Hi,

I just got my board (sweet!). I just got one to play around with but looking at it gave me an idea...

I am looking into the feasibility of using the parallella to receive data from an ADC and storing that data locally.

The ADC I have in mind is: ADS5474 which is a 14-bit, 400-MSPS analog-to-digital converter (ADC).[ ref: http://www.ti.com/product/ads5474] . The ADC would generate data at 800MBps. To interface the 2 I'd have to build a custom daughter card of course (and work out the pin conversions!). Anyway, Table 19 in the reference manual says the PEC_FPGA port has a peak b/w of 2.8GBps. What is the sustained b/w over this port?

Also, since the ADC will present 800MBps, I have to be able to store the data at that speed too. What are my options for this?

Thanks in advance.
sneuf0897
 
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Re: High speed data aquistion and storage

Postby FHuettig » Tue Aug 05, 2014 10:42 pm

sneuf0897 wrote:...Table 19 in the reference manual says the PEC_FPGA port has a peak b/w of 2.8GBps. What is the sustained b/w over this port?


That number is just the maximum rate of the LVDS buffers on the Zynq (950Mb/s), times 24 available pairs (3 bytes) = 2.85GB/s. It doesn't relate to anything that has been implemented in the Parallella logic or Arm driver, nor does it allow for a clock signal. So for your use it would be possible to sustain up to 1.9MB/s through the IO pads (2 bytes * 950Mb/s), but it's up to you to do something with that data once it gets into the FPGA fabric. The current Parallella FPGA design connects those pins as single-ended GPIOs, and the standard "bit-bang" driver is really quite slow.

sneuf0897 wrote:Also, since the ADC will present 800MBps, I have to be able to store the data at that speed too. What are my options for this?


If you need to capture full-rate full-resolution data the only option is to dump it right to SDRAM, into a pre-allocated buffer, so you'll be limited to less than a second of data before you have to process it and/or store it to the SDcard or over Ethernet. To do this you'll have to connect the inputs to an AXI port and set up a DMA engine to move the data into the buffer as it comes in. From that point there should be enough bandwidth to the SDRAM to keep up, I think the DDR is set for 4.26GB/s peak.
-- Fred -- Hardware Guy --
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Re: High speed data aquistion and storage

Postby sneuf0897 » Wed Aug 06, 2014 8:51 pm

@Fred
Thanks for the info.

FHuettig wrote: So for your use it would be possible to sustain up to 1.9MB/s through the IO pads (2 bytes * 950Mb/s), but it's up to you to do something with that data once it gets into the FPGA fabric.


Ok, my ADC will generate 0.8GB/s and the GPIO port will support up to 1.9GB/s using my scheme (2 bytes * 950Mb/s)...so far so good.

FHuettig wrote:If you need to capture full-rate full-resolution data the only option is to dump it right to SDRAM, into a pre-allocated buffer, so you'll be limited to less than a second of data before you have to process it and/or store it to the SDcard or over Ethernet. To do this you'll have to connect the inputs to an AXI port and set up a DMA engine to move the data into the buffer as it comes in. From that point there should be enough bandwidth to the SDRAM to keep up, I think the DDR is set for 4.26GB/s peak.


Other than saving the data to SD card/ Eth, how about leveraging the PEC_North/South ports (their peak performance is 2.6GB/s)? Is the main challenge there that its DIY hardware ...and for a hobbyist that'd be going overboard? ;)

Thanks.
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