Parallella Memory

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

Re: Parallella Memory

Postby timpart » Sat Nov 29, 2014 10:06 am

notzed wrote:
aolofsson wrote:Just so that we are clear regarding point #2.

The following scenario is a gotcha!

1.) CoreA writes aa to addr X
2.) CoreA reads from addr X
3.) CoreA write bb to addr X

The value read back in step 2 could be aa or bb, depending on network traffic. Very likely that aa is returned, but not guaranteed

This is only an issue when X is outside coreA

Doesn't 2 stall until it returns? Or does that stall not prevent step 3 getting far enough through the pipeline to fire off the write transaction?

This is a surprise to me too! Perhaps the read is initiated but doesn't cause a stall, with the receiving register just being marked as "busy". A subsequent use of that register by a later instruction would stall until the read completes.

Since reads are much slower than writes, I wonder if bb is actually the more likely scenario even with no network congestion if the second write is immediately after the read.
Is it possible to stop this bb issue by using

notzed wrote:Is there a 3rd possibility that it gets neither aa or bb (whatever was there before)?

I'd agree if the write network was very congested. Also the code I gave above doesn't fix this issue.

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Re: Parallella Memory

Postby aolofsson » Sat Nov 29, 2014 11:25 am

Sorry for the confusion!! I edited the original comment to try to clarify. The original example applies only to DMA. "LDR instructions" are blocking. Still, the example below is a real problem.

[edit: New example]
A more likely scenario is the following:
0.) CoreA writes aa to addr X
....a lot of other stuff happens
1.) CoreA writes bb to addr X
2.) CoreA reads from addr X

Lesson, don't set some kind of program status/sync flag outside of local memory, without doing an explicit path flush as described here:
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Re: Parallella Memory

Postby greytery » Sat Nov 29, 2014 1:41 pm

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