Epiphany NoC simulator

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Epiphany NoC simulator

Postby joaofl » Mon Sep 07, 2015 3:06 pm

I've been working with Network Simulators using NS3, more specifically mesh grid networks of chips.

I was wondering if the Parallella community have interest on an open-source simulator of the Epiphany NoC (eMesh) based on NS3, and what features one would expect to have there. In other words, which metrics to extract, and which scenarios to simulate.

It is already under development, and comments and contributions are very welcome.

The Epiphany Chip should be the first one to be implemented in order to validate the simulator.

Work done so far can be seen at: https://bitbucket.org/joaofl/noc

Thanks in advance.

Best,

João Loureiro
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Re: Epiphany NoC simulator

Postby jar » Tue Sep 08, 2015 1:55 pm

I would be most interested in a comparison between 16 and 64 core network performance (since most people don't have 64 cores) for various communication patterns (raster scan, rotate east/west/north/south, random, etc). I would also like a comparison to a much larger NoC. It would be good to know when the bandwidth/latency performance turns over for DMA and memory mapped access for both read and write operations (eventually, DMA is always faster, but how much data?). And if you're a glutton for punishment, performance of hypothetical tiled NoCs.

I would be interested in reading about your simulation results and how they compare to hardware (at least the 16-core NoC)
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Re: Epiphany NoC simulator

Postby joaofl » Tue Sep 08, 2015 4:14 pm

jar wrote:I would be most interested in a comparison between 16 and 64 core network performance (since most people don't have 64 cores) for various communication patterns (raster scan, rotate east/west/north/south, random, etc). I would also like a comparison to a much larger NoC. It would be good to know when the bandwidth/latency performance turns over for DMA and memory mapped access for both read and write operations (eventually, DMA is always faster, but how much data?). And if you're a glutton for punishment, performance of hypothetical tiled NoCs.

I would be interested in reading about your simulation results and how they compare to hardware (at least the 16-core NoC)


Thanks for your opinion. I plan to come to this comparison, exactly. Although it is hard to model the use of DMA in a core, since my model should take care of the network only, and not the time the processor takes to put the data on the network. I'm still not sure of how could I model that, or if it is interesting to do it, since we are interested on the restriction imposed by the nw only (processing happens instantly).

My objective is exactly to expand the concept of a NoC like Epiphany, to a huge mesh grid of sensor nodes, to see how distributed processing could work out in this distinct scenario, which also imposes different restriction and opportunities. I have published a simulation result of a 101x101 mesh grid network, but using different packet structures, network architecture and rates. Now I would like to approach that simulation to what a real hardware could really do.

Ill consider ur points.

Thanks a lot.
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