Start Address for Cores?

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Start Address for Cores?

Postby etim » Wed Sep 23, 2015 8:56 pm

The only reference for the start address for the cores is here: Is this always accurate for all 16-core chips?

Do we need to hardcode these addresses or is there a way to generate them given core row and col?
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Re: Start Address for Cores?

Postby sebraa » Wed Sep 23, 2015 9:56 pm

The base address of a core is given by putting the row and col numbers into the upper 12 bits of the address (6 bits row, 6 bits col).
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Re: Start Address for Cores?

Postby etim » Thu Sep 24, 2015 8:31 pm

Thanks. I also see that the row and col are hardcoded in the HDF file.

The Epiphany chip is situated within a 1GB section within the Zynq host processor memory
map. The offset within the 1GB space occupied by an Epiphany coprocessor is set by the
ROWID and COLID pins on the Epiphany chip. The ROWID and COLID can be individually
set on boards through the PEC_POWER connector enabling direct board to board connection
through the PEC_NORTH and PEC_SOUTH connectors. By default the address locations of the
Epiphany cores on Parallella-16 are as shown in the Table below.

Chip Core Number Start Address End Address Size
(32,8) 80800000 80807FFF 32KB
(32,9) 80900000 80907FFF 32KB
(32,10) 80A00000 80A07FFF 32KB
(32,11) 80B00000 80B07FFF 32KB
(33,8) 84800000 84807FFF 32KB
(33,9) 84900000 84907FFF 32KB
(33,10) 84A00000 84A07FFF 32KB
(33,11) 84B00000 84B07FFF 32KB
(34,8) 88800000 88807FFF 32KB
(34,9) 88900000 88907FFF 32KB
(34,10) 88A00000 88A07FFF 32KB
(34,11) 88B00000 88B07FFF 32KB
(35,8) 8C800000 8C807FFF 32KB
(35,9) 8C900000 8C907FFF 32KB
(35,10) 8CA00000 8CA07FFF 32KB
(35,11) 8CB00000 9CB07FFF 32KB
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