Is there power gating for each core?

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Is there power gating for each core?

Postby guoxinfei » Wed Nov 18, 2015 6:46 pm

I am new to parallella. I read through the Epiphany Architecture Reference, and found there are two low power modes during IDLE, 0=Minimal clock gating in idle mode (high power) and 1=Aggressive power down in idle mode (recommended). I wonder what are the differences in terms of hardware implementations? Is the first one just gate several clock path and the second one gate all the clocks? Is there power gating for each core? Basically, I am trying to figure out if I have control of the power of each core.

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