Interrupt information needed

[alexrp]

[timpart]

I got that impression too. As soon as the interrupt situation arises EXCAUSE is written to and the interrupt happens. SWI is an instruction that triggers an interrupt, in a similar way to SYNC and WAND. (SWI is also quite close to TRAP but causes an interrupt rather than halting the processor.)

Tim

[aolofsson]

Tim, you are correct in your interpretation. The only thing SWI does is generate an interrupt. One could imagine a similar implementation to the current TRAP based one for system calls.(but without the need for a host).

[alexrp]

[timpart]

[EggBaconAndSpam]

First of all: according to the Architecture Reference, a non-zero EXCAUSE does actually trigger an interrupt! (See p.47)

Also, don't write to EXCAUSE!
EXCAUSE is merely used by to differentiate between the following:misaligned load/store,FPU exception, unimplemented, no exception and so on
Rather, use SWI in conjunction with general purpose registers, as is common on x86 and arm platforms, such that a software interrupt handler may differentiate between: a) Something _really_ bad happened (EXCAUSE != 1)
b) a syscall (EXCAUSE==1), in this case check the relevant gp-registers (a good idea would be to simply adopt the standard calling convention, with the exception of using IRET instead of the link register)

//edit I was using an outdated reference manual, why the hell does the link on adapteva.com still point to http://www.adapteva.com/wp-content/uplo ... .12.18.pdf ?

[timpart]

[alexrp]

[alexrp]

@aolofsson ping on the question of whether writing to EXCAUSE with MOVTS (or similar) should raise an interrupt. :)

[aolofsson]

Sorry for the slow reply...

Q. Does writing to EXCAUSE immediately cause a software exception to be generated? I.e. you wouldn't have to 'trigger' it with SWI or something similar? In this case, what purpose will SWI serve when it's published fully?

A: Yes. writing to EXCAUSE does cause a software exception, but this really is not the intended (or tested use case). Maybe we can save this discussion for later. We do have some overlap of features, but as a minimum the SWI enables a cleaner implementation of a system call than writing to the excause register.It always gets confusing when there is more than one way to implement functionality..

Q. When is EXCAUSE reset by the hardware, if at all?

A: The excause is reset by the core reset or by clearing the bits by writing to the STATUS register.