Manual should specify what RTI does outside of an ISR

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Re: Manual should specify what RTI does outside of an ISR

Postby timpart » Sun Dec 22, 2013 1:08 pm

Thanks Andreas that is helpful.

I especially note your mention of GID and GIE. Currently the C compiler generates these around a change of arithmetic mode (floating point vs integer). I'm not sure why. It could only protect against an interrupt service routine making a permanent change to CONFIG and that change getting lost by the user code changing CONFIG. I can't offhand think of any reason why a randomly happening ISR would want to make a permanent change to CONFIG. Some change of a timer mode?!

Off topic, I hope everyone here has restful holidays which are fun and a complete break from work.

Tim
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Re: Manual should specify what RTI does outside of an ISR

Postby aolofsson » Mon Dec 23, 2013 1:41 am

Thanks Tim!

Not sure what our reasoning was?? I can check in with @amylaar who wrote the GCC compiler code. I think this might have been an old "safety measure" that we didn't need in the end. Can you add an issue to gcc? (I would be happy to do it myself, but you should have the honors:-) Note that there is no such code in the elib register read/write function call.

Have a great holiday everyone!

Andreas
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Re: Manual should specify what RTI does outside of an ISR

Postby Urhixidur » Thu Feb 26, 2015 7:48 pm

aolofsson wrote:This is what happens when an RTI instruction is executed:
[...]
3.) The IPEND bit of the ISR currently being executed is cleared. If the IPEND register is all zero (no ISR), there is nothing to clear.

"The IPEND bit of the ISR currently being executed" is the lowest IPEND bit, if I read the Epiphany Architecture Reference entry for IPEND (p. 144 in rev 14.03.11) correctly. If I understand correctly, an interrupt will occur only if a) it is latched (its bit in ILAT is on), b) it is not masked (its bit in IMASK is off), and c) it is not pre-empted by a higher-priority interrupt in progress (the lowest on bit of IPEND, if any, is higher than the interrupt's own). In which order are these conditions checked? Or are they simultaneous?
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Re: Manual should specify what RTI does outside of an ISR

Postby timpart » Sat Mar 21, 2015 10:17 pm

Urhixidur wrote:"The IPEND bit of the ISR currently being executed" is the lowest IPEND bit, if I read the Epiphany Architecture Reference entry for IPEND (p. 144 in rev 14.03.11) correctly. If I understand correctly, an interrupt will occur only if a) it is latched (its bit in ILAT is on), b) it is not masked (its bit in IMASK is off), and c) it is not pre-empted by a higher-priority interrupt in progress (the lowest on bit of IPEND, if any, is higher than the interrupt's own). In which order are these conditions checked? Or are they simultaneous?


I think it all happens together in the hardware. Andreas once generously published some of the interrupt related Verilog. The first statement is a long ANDing of the various registers involved.

Tim
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