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Parallella Community • View topic - Unaligned access semantics

Unaligned access semantics

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

Unaligned access semantics

Postby alexrp » Thu Jan 02, 2014 7:11 am

So the manual does specify what happens on unaligned reads and writes, but a couple of things are missing:

1. Do unaligned reads return *sensible* values or garbage?
2. At what stage during its operation does TESTSET raise a software exception?

And on a somewhat related note, is a simulator allowed to just not perform an unaligned write or return any value(s) for an unaligned read? Assuming both unaligned reads and writes result in garbage, this seems like it would adhere to the documentation (leaving old values in place could be seen as garbage).
Last edited by alexrp on Thu Jan 02, 2014 9:22 am, edited 1 time in total.
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Re: Unaligned access semantics

Postby timpart » Thu Jan 02, 2014 7:56 am

My personal view is that it will return whatever falls out of that particular chip's logic. It will probably have some data from a nearby location. That could change from one chip version to another though. At least they are kind enough to raise an interrupt. Some chips just silently return garbage.

So I'd say it doesn't really matter what a simulator does in terms of data. The operation is undefined in terms of data content. You could however overwrite with some unusual but obvious bit pattern like 0x0bad. That way it is less confusing to someone debugging. (The current value of the register may be a plausible value which can be much harder to spot than an obviously wrong one.)

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Re: Unaligned access semantics

Postby aolofsson » Thu Jan 02, 2014 3:48 pm

Unaligned reads return garbage, but to be honest we have not done a lot of testing of this, so it may cause "undefined behavior". Same thing for writes.
The TESTSET, like the LDR/STR throws an exception at the E1 pipeline stage on unaligned access. (even if the LDR/TESTSET access if to remote memory where the return latency could be 100's of clock cycles).
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Re: Unaligned access semantics

Postby notzed » Tue Jul 01, 2014 5:24 am

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Re: Unaligned access semantics

Postby timpart » Tue Jul 01, 2014 12:01 pm

I recall Andreas saying there is an erratum with the E16G301 chip in that it halts after going into the software exception interrupt. However I can't find the post. Perhaps Andreas can confirm or deny?

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Re: Unaligned access semantics

Postby aolofsson » Tue Jul 01, 2014 1:10 pm

Tim,notzed:

That's right, software exceptions hang on address 0x4. The full errata documented in the E16G301 datasheet.
(http://adapteva.com/docs/e16g301_datasheet.pdf)

There aren't too many, but this is one of them...

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