Hardware loops and IDLE/TRAP

[alexrp]

I'm wondering what happens if an IDLE instruction is issued inside a hardware loop? I would imagine, since interrupts are disabled, that it would just effectively leave the core in an unusable state, but are there any other things worth being aware of? Similarly, I'm wondering how TRAP interacts with all this.

[timpart]

I don't think hardware loops are special in this circumstance. As you have identified it is the disabling of interrupts that is crucial.

With IDLE I imagine the only "interrupt" that will get through is the reset wire or a core reset via the appropriate register.
With TRAP an external controller could notice and after doing something start the core running again.

I wouldn't expect either to be used inside a hardware loop in practice.

Tim

[aolofsson]

There is no special interrupt disable mechanism when inside a hardware loop, but there is a restriction that the GID bit in the STATUS has to be set before entering a loop. The hardware limitation is that if an interrupt happens when the sequencer is in the middle of a hardware loop, bad "undefined" things happen. I can't remember how good the trap support is for hardware loops, but it's very lightly tested, so there may be issues..

Hardware Loop Disclaimer:
This feature will always have a "beta" stamp on it and is really only meant for assembly programmers with tough skin.