Comments on the FPGA code

[tnt]

Hi,

I've been spending the day trying to get a FPGA code build on Vivado 2013.4 for the Gen0 & Gen1 boards I have. When playing around with it, I have a few comments to improve it :

* Some of the verilog files are missing proper `include directives to get version.v and fpga_constants.v in the context

* I would rename a lot of the objects to have a consistent prefix for all elink stuff. axi_master is a bit generic especially when you have other logic in it that just the elink stuff

* The naming convention for the e-link external pins is just weird and inconsistent. At the fpga top level, they're essentially the exact name of the epiphany pin they're connected to. That's a fine convention, but when you dig a bit, the parallella.v module conventions are just confusing.
- There is only rxi_ and txo_ (no rxo or txi) no matter if the pin is an input or an output.
- Usually you need to connect the rx?_* ports to the tx?_* pads of the fpga, which make sense (the convention 'swap' between epiphany side and fpga side done in the top level). _EXCEPT_ for the rxi_cclk_p ... which doesn't change ... I understand that this is the chip clock and a bit special but then maybe it's port name should be distinct from the e-link {rx,tx}{i,o} convention ...

* I would split off the actual IO Buffers into a dedicated module to be instanciated near the top level. This would allow to deal more easily with gen0/gen1 difference. For now I just added a module parameter to select between Gen0 and Gen1 implementation so the same code can support both.

* No ISERDES ? Seems that logic is somehow implemented manually, while for the output, it uses OSERDES. Any reason for this


Cheers,

Sylvain