by aolofsson » Mon Dec 15, 2014 1:20 pm
Sorry for the slow reply!
The cmesh can transfer 8 bytes/cycle at each node in each direction. At 600Mhz this implies a peak bandwidth of 4.8GB/s. However, due two errata items, the DMA bandwidth out of one core is limited to ~25% of this. This is documented in the datasheet of the processor E16G301 and E64G401. As regrettable as this is, we have found the existing on chip bandwidth to be the least of our problems. (see FFT and matmul benchmarks on github for examples showing effective on chip communication patterns). The 1.2GB/s is still much higher than the off chip bandwidth.
What are you trying to test?
Andreas