Can Epiphany III core be blocked from writing to host mem?

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Can Epiphany III core be blocked from writing to host mem?

Postby rowan194 » Wed Jan 28, 2015 9:33 pm

According to the Epiphany Architecture Reference page 146, for the Epiphany III only bits 0-7 of the MEMPROTECT register are functional. From my understanding, this means that I can set the core to "read only", disallowing writes from other cores (and possibly the host?), but only the Epiphany IV will let me prevent a given core from writing out to other cores, or host memory. I can set all cores to read-only, which will protect them from each other, but there seems to be no way to prevent a core from writing to host memory on the Epiphany III.

I want to experiment with free-for-all execution, where each core basically starts with binary junk, and through successive empirical testing eventually evolve their machine code to do something useful, but this is risky if a core happens to execute a series of instructions that write to host memory. If this happens, the whole board could lock up, or even worse, go unstable via subtle corruption. It needs to be protected because each core is executing random code.

tl;dr is there any way to prevent cores from writing to the host memory on the Parallella with Epiphany III?
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Re: Can Epiphany III core be blocked from writing to host me

Postby greytery » Thu Jan 29, 2015 9:25 am

AFAIK the only way that the epiphany can access the main host memory is via the East eLink, implemented in the FPGA.
Currently that is limited to the top 32MB of the 1GB Host memory and refered to as 'shared memory'.
That is policed by the piece of "magical" address translation refered to by Andreas at https://parallella.org/forums/viewtopic.php?f=13&t=1226&start=10&sid=caa7040421d0eb0650d1bb9cf99ef787&sid=caa7040421d0eb0650d1bb9cf99ef787#p7797.
Any attempt at addressing outside that 32MB mapped area ends up on the north, south or west elink interfaces (i.e. thin air) or undefined (which is probably where your worries start).

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Re: Can Epiphany III core be blocked from writing to host me

Postby rowan194 » Thu Jan 29, 2015 11:10 am

Yeah, looks like it's going to be hard to start with random garbage. From a quick look at the Epiphany instruction decode format, it looks like it may be possible to use all 32 bit instructions (so every instruction is a consistent size and the code doesn't need to be traced), which will allow me to limit use of register to memory instructions, disallowing access to any external memory.

Shouldn't be much harder to generate random instructions, rather than just load random bytes into the Epiphany.

edit: Argh, I didn't look closely enough, there are several register to register instructions, such as ADD, that are 16 bits only. I guess I'll have to marry those with a NOP, and align any jumps to 32 bit words. Getting more complicated...
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Re: Can Epiphany III core be blocked from writing to host me

Postby timpart » Mon Feb 23, 2015 12:34 pm

rowan194 wrote:Argh, I didn't look closely enough, there are several register to register instructions, such as ADD, that are 16 bits only. I guess I'll have to marry those with a NOP, and align any jumps to 32 bit words. Getting more complicated...


The 16 bit register instructions normally have a long equivalent e.g. ADD.L that forces them to be 32 bit. I think only the system stuff like turning interrupts on and off, RTS, RTI, NOP are 16 bit only. (Though there is a special form of NOP around as well designed to achieve 64 bit alignment of hardware loops.) See appendix C and hardware loop section of the Arch Ref manual for more info.

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