FPGA Accelerator

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

FPGA Accelerator

Postby promach » Tue Jan 03, 2017 7:47 am

I am having error http://paste2.org/ZtgJm29N with https://www.parallella.org/2016/01/21/creating-an-fpga-accelerator-in-15-minutes/ . Anyone ?

The error is due to the "WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins
INFO: [Synth 8-256] done synthesizing module 'system_wrapper' (2#1) [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12]"

Image

[promach@localhost oh]$ cd src/accelerator/fpga/
[promach@localhost fpga]$ ./build.sh
rm: cannot remove 'system_wrapper.bit.bin': No such file or directory
rm: cannot remove 'bit2bin.bin': No such file or directory

****** Vivado v2016.2 (64-bit)
**** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
**** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source package.tcl
# source ./ip_params.tcl
## set design axi_accelerator
## set projdir ./
## set root "../.."
## set partname "xc7z020clg400-1"
## set hdl_files [list \
## $root/accelerator/hdl \
## $root/common/hdl/ \
## $root/emesh/hdl \
## $root/emmu/hdl \
## $root/axi/hdl \
## $root/emailbox/hdl \
## $root/edma/hdl \
## $root/elink/hdl \
## ]
## set ip_files []
## set constraints_files []
# source ../../common/fpga/create_ip.tcl
## create_project -force $design $projdir -part $partname
## set_property target_language Verilog [current_project]
## set_property source_mgmt_mode None [current_project]
## if {[string equal [get_filesets -quiet sources_1] ""]} {
## create_fileset -srcset sources_1
## }
## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
## set_property top $design [get_filesets sources_1]
## if {[string equal [get_filesets -quiet constraints_1] ""]} {
## create_fileset -constrset constraints_1
## }
## if {[llength $constraints_files] != 0} {
## add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files
## }
## if {[llength $ip_files] != 0} {
##
## #Add to fileset
## add_files -norecurse -fileset [get_filesets sources_1] $ip_files
##
## #Set mode for IP
## foreach file $ip_files {
## #TODO: is this needed?
## set file_obj [get_files -of_objects [get_filesets sources_1] $file]
## set_property "synth_checkpoint_mode" "Singular" $file_obj
## }
## #RERUN/UPGRADE IP
## upgrade_ip [get_ips]
## }
## ipx::package_project -import_files -force -root_dir $projdir
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockgate.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_abs.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_isohi.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_iddr.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_datagate.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_delay.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_isolo.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux2.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux12.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_crc.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux8.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_add.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_shifter.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_8b10b_decode.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_8b10b_encode.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa92.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_buf.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_lat0.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa62.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_tristate.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pulse2pulse.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockdiv.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/cfg_generic.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_crc32_64b.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_stretcher.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_gray2bin.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_ser2par.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_rsync.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_counter.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa42.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_reg0.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_edge2pulse.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux4.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_bitreverse.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_crc32_8b.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pll.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_reg1.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_oddr.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_standby.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fifo_async.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_bin2gray.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux6.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_par2ser.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_rise2pulse.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fall2pulse.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fifo_cdc.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_lat1.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_debouncer.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux9.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_bin2onehot.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockmux.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_edgedetect.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_7seg_decode.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_parity.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_memory_sp.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fifo_generic.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa32.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockor.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux5.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux7.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_gate.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux3.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_buffer.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_edgealign.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_constants.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_rdalign.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/ememory.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_wralign.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_if.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_readback.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emmu/hdl/emmu.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emailbox/hdl/emailbox_regmap.vh'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emailbox/hdl/emailbox.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_dp.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_regs.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_ctrl.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_regmap.vh'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_arbiter.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/ecfg_if.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/axi_elink.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_core.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_clocks.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_clocks.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink_constants.vh'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_protocol.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink_cfg.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_io.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink_regmap.vh'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_fifo.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_remap.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_remap.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_arbiter.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_core.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_fifo.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_io.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink.v'.
INFO: [Common 17-14] Message 'IP_Flow 19-3833' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.2/data/ip'.
CRITICAL WARNING: [HDL 9-870] Macro <CFG_ASIC> is not defined. [src/oh_memory_dp.v:36]
CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_memory_dp.v:36]
CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_dsync.v:18]
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/accelerator_regmap.vh" from the top-level HDL file.
INFO: [IP_Flow 19-2228] Inferred bus interface 'm_axi' of definition 'xilinx.com:interface:aximm:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'm_axi_aresetn' as interface 'm_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4753] Inferred signal 'interrupt' from port 'irq' as interface 'irq'.
INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'sys_clk' as interface 'sys_clk'.
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((2 * spirit:decode(id('MODELPARAM_VALUE.AW'))) + 40)" into user parameter "PW".
## ipx::remove_memory_map {s_axi} [ipx::current_core]
## ipx::add_memory_map {s_axi} [ipx::current_core]
## ipx::associate_bus_interfaces -busif s_axi -clock sys_clk [ipx::current_core]
INFO: [IP_Flow 19-4728] Bus Interface 'sys_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
## ipx::associate_bus_interfaces -busif m_axi -clock sys_clk [ipx::current_core]
WARNING: command 'get_bus_interface' will be removed in the 2015.3 release, use 'get_bus_interfaces' instead
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]]
WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead
## ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]]
WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead
WARNING: command 'get_address_block' will be removed in the 2015.3 release, use 'get_address_blocks' instead
## set_property range {65536} [ipx::get_address_block axi_lite \
## [ipx::get_memory_map s_axi [ipx::current_core]]]
## set_property vendor {www.parallella.org} [ipx::current_core]
## set_property library {user} [ipx::current_core]
## set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
## set_property vendor_display_name {ADAPTEVA} [ipx::current_core]
## set_property company_url {www.parallella.org} [ipx::current_core]
## set_property supported_families { \
## {virtex7} {Production} \
## {qvirtex7} {Production} \
## {kintex7} {Production} \
## {kintex7l} {Production} \
## {qkintex7} {Production} \
## {qkintex7l} {Production} \
## {artix7} {Production} \
## {artix7l} {Production} \
## {aartix7} {Production} \
## {qartix7} {Production} \
## {zynq} {Production} \
## {qzynq} {Production} \
## {azynq} {Production} \
## } [ipx::current_core]
WARNING: [IP_Flow 19-4623] Unrecognized family virtex7. Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-4623] Unrecognized family qvirtex7. Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-4623] Unrecognized family kintex7. Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-4623] Unrecognized family kintex7l. Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7. Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7l. Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-4623] Unrecognized family artix7. Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-4623] Unrecognized family artix7l. Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-4623] Unrecognized family aartix7. Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-4623] Unrecognized family qartix7. Please verify spelling and reissue command to set the supported files.
## ipx::archive_core [concat $design.zip] [ipx::current_core]
## exit
INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:11:58 2017...

****** Vivado v2016.2 (64-bit)
**** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
**** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source run.tcl
# source ./run_params.tcl
## set design system
## set projdir ./
## set partname "xc7z020clg400-1"
## set ip_repos [list "."]
## set hdl_files []
## set constraints_files []
# source ../../common/fpga/system_init.tcl
## create_project -force $design $projdir -part $partname
## set_property target_language Verilog [current_project]
## set report_dir $projdir/reports
## set results_dir $projdir/results
## if ![file exists $report_dir] {file mkdir $report_dir}
## if ![file exists $results_dir] {file mkdir $results_dir}
## set other_repos [get_property ip_repo_paths [current_project]]
## set_property ip_repo_paths "$ip_repos $other_repos" [current_project]
## update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.2/data/ip'.
## create_bd_design "system"
Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
## source $projdir/system_bd.tcl
### namespace eval _tcl {
### proc get_script_folder {} {
### set script_path [file normalize [info script]]
### set script_folder [file dirname $script_path]
### return $script_folder
### }
### }
### variable script_folder
### set script_folder [_tcl::get_script_folder]
### set scripts_vivado_version 2016.2
### set current_vivado_version [version -short]
### if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
### puts ""
### catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
###
### return 1
### }
### set list_projs [get_projects -quiet]
### if { $list_projs eq "" } {
### create_project project_1 myproj -part xc7z020clg400-1
### }
### set design_name system
### set errMsg ""
### set nRet 0
### set cur_design [current_bd_design -quiet]
### set list_cells [get_bd_cells -quiet]
### if { ${design_name} eq "" } {
### # USE CASES:
### # 1) Design_name not set
###
### set errMsg "Please set the variable <design_name> to a non-empty value."
### set nRet 1
###
### } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
### # USE CASES:
### # 2): Current design opened AND is empty AND names same.
### # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
### # 4): Current design opened AND is empty AND names diff; design_name exists in project.
###
### if { $cur_design ne $design_name } {
### common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
### set design_name [get_property NAME $cur_design]
### }
### common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
###
### } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
### # USE CASES:
### # 5) Current design opened AND has components AND same names.
###
### set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
### set nRet 1
### } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
### # USE CASES:
### # 6) Current opened design, has components, but diff names, design_name exists in project.
### # 7) No opened design, design_name exists in project.
###
### set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
### set nRet 2
###
### } else {
### # USE CASES:
### # 8) No opened design, design_name not in project.
### # 9) Current opened design, has components, but diff names, design_name not in project.
###
### common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
###
### create_bd_design $design_name
###
### common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
### current_bd_design $design_name
###
### }
INFO: [BD_TCL-2] Constructing design in IPI design <system>...
### common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "system".
### if { $nRet != 0 } {
### catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
### return $nRet
### }
### proc create_root_design { parentCell } {
###
### variable script_folder
###
### if { $parentCell eq "" } {
### set parentCell [get_bd_cells /]
### }
###
### # Get object for parentCell
### set parentObj [get_bd_cells $parentCell]
### if { $parentObj == "" } {
### catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
### return
### }
###
### # Make sure parentObj is hier blk
### set parentType [get_property TYPE $parentObj]
### if { $parentType ne "hier" } {
### catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
### return
### }
###
### # Save current instance; Restore later
### set oldCurInst [current_bd_instance .]
###
### # Set parent object as current
### current_bd_instance $parentObj
###
###
### # Create interface ports
###
### # Create ports
###
### # Create port connections
###
### # Create address segments
###
###
### # Restore current instance
### current_bd_instance $oldCurInst
###
### save_bd_design
### }
### create_root_design ""
## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v
Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
## if {[string equal [get_filesets -quiet sources_1] ""]} {
## create_fileset -srcset sources_1
## }
## set top_wrapper $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
## add_files -norecurse -fileset [get_filesets sources_1] $top_wrapper
## if {[llength $hdl_files] != 0} {
## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
## }
## if {[string equal [get_filesets -quiet constrs_1] ""]} {
## create_fileset -constrset constrs_1
## }
## if {[llength $constraints_files] != 0} {
## add_files -norecurse -fileset [get_filesets constrs_1] $constraints_files
## }
# source ../../common/fpga/system_build.tcl
## validate_bd_design
INFO: [BD 5-320] Validate design is not run, since the design is already validated.
## write_bd_tcl -force ./system_bd.tcl
INFO: [BD 5-148] Tcl file written out </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system_bd.tcl>.

## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v
Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
## remove_files -fileset sources_1 $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
## add_files -fileset sources_1 -norecurse $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
## if {[info exists oh_synthesis_options]} {
## puts "INFO: Synthesis with following options: $oh_synthesis_options"
## set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $oh_synthesis_options -objects [get_runs synth_1]
## }
## launch_runs synth_1
INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v
Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
Exporting to file /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system.hwh
Generated Block Design Tcl file /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
Generated Hardware Definition File /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.hwdef
[Tue Jan 3 15:12:07 2017] Launched synth_1...
Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/synth_1/runme.log
## wait_on_run synth_1
[Tue Jan 3 15:12:07 2017] Waiting for synth_1 to finish...

*** Running vivado
with args -log system_wrapper.vds -m64 -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl


****** Vivado v2016.2 (64-bit)
**** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
**** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source system_wrapper.tcl -notrace
Command: synth_design -top system_wrapper -part xc7z020clg400-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 32612
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1006.043 ; gain = 124.121 ; free physical = 136 ; free virtual = 3622
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'system_wrapper' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12]
INFO: [Synth 8-638] synthesizing module 'system' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v:13]
INFO: [Synth 8-256] done synthesizing module 'system' (1#1) [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v:13]
WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins
INFO: [Synth 8-256] done synthesizing module 'system_wrapper' (2#1) [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1045.480 ; gain = 163.559 ; free physical = 124 ; free virtual = 3582
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1045.480 ; gain = 163.559 ; free physical = 124 ; free virtual = 3582
---------------------------------------------------------------------------------
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1337.918 ; gain = 0.000 ; free physical = 142 ; free virtual = 3432
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for system_i. (constraint file auto generated constraint, line ).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
---------------------------------------------------------------------------------
WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 139 ; free virtual = 3431
---------------------------------------------------------------------------------
Start Cross Boundary Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 139 ; free virtual = 3431
---------------------------------------------------------------------------------
Finished Parallel Reinference : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 139 ; free virtual = 3431

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 131 ; free virtual = 3423
---------------------------------------------------------------------------------
Finished Parallel Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 131 ; free virtual = 3423

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1354.902 ; gain = 472.980 ; free physical = 140 ; free virtual = 3386
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1354.902 ; gain = 472.980 ; free physical = 140 ; free virtual = 3386
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 132 ; free virtual = 3378
---------------------------------------------------------------------------------
Finished Parallel Technology Mapping Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 132 ; free virtual = 3378

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 132 ; free virtual = 3378
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+------+--------------+----------+
| |BlackBox name |Instances |
+------+--------------+----------+
|1 |system | 1|
+------+--------------+----------+

Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |system | 1|
+------+-------+------+

Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 0|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1363.918 ; gain = 104.434 ; free physical = 131 ; free virtual = 3377
Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.926 ; gain = 482.004 ; free physical = 131 ; free virtual = 3377
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
13 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1364.918 ; gain = 410.457 ; free physical = 130 ; free virtual = 3377
report_utilization: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1372.922 ; gain = 0.000 ; free physical = 129 ; free virtual = 3377
INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:12:31 2017...
[Tue Jan 3 15:12:34 2017] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:27 . Memory (MB): peak = 1070.695 ; gain = 8.000 ; free physical = 619 ; free virtual = 3868
## launch_runs impl_1
[Tue Jan 3 15:12:34 2017] Launched impl_1...
Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/impl_1/runme.log
## wait_on_run impl_1
[Tue Jan 3 15:12:34 2017] Waiting for impl_1 to finish...

*** Running vivado
with args -log system_wrapper.vdi -applog -m64 -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace


****** Vivado v2016.2 (64-bit)
**** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
**** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source system_wrapper.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2016.2
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'system_i' of type 'system_i/system' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
INFO: [Project 1-461] DRC finished with 1 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1280.484 ; gain = 66.031 ; free physical = 222 ; free virtual = 3489
INFO: [Common 17-83] Releasing license: Implementation
10 Infos, 0 Warnings, 1 Critical Warnings and 2 Errors encountered.
opt_design failed
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:12:44 2017...
[Tue Jan 3 15:12:46 2017] impl_1 finished
wait_on_run: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:12 . Memory (MB): peak = 1070.695 ; gain = 0.000 ; free physical = 597 ; free virtual = 3865
## launch_runs impl_1 -to_step write_bitstream
[Tue Jan 3 15:12:46 2017] Launched impl_1...
Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/impl_1/runme.log
## wait_on_run impl_1
[Tue Jan 3 15:12:46 2017] Waiting for impl_1 to finish...
[Tue Jan 3 15:12:46 2017] impl_1 finished
INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:12:46 2017...
[ERROR] : Can't read BIT file - ./system.runs/impl_1/system_wrapper.bit
cp: cannot stat 'system_wrapper.bit.bin': No such file or directory
[promach@localhost fpga]$
promach
 
Posts: 6
Joined: Mon Dec 12, 2016 9:03 am

Re: FPGA Accelerator

Postby jvarred » Sun Apr 30, 2017 10:43 pm

Hi, I had the same problem and it solved after changing vivado version on system_bd.tcl file (https://github.com/parallella/oh/issues/98). I reccomend you to use the stable branch as it doesn't give those problems. Here are the steps that I used to make it work: https://github.com/parallella/oh/issues ... -298262178
jvarred
 
Posts: 1
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Re: FPGA Accelerator

Postby promach » Fri Jun 09, 2017 9:00 am

I am using Vivado version 2017.1

I have followed the instructions in https://github.com/parallella/oh/issues/103#issuecomment-298262178, but I still have the following error.

[ERROR] : Can't read BIT file - ./system.runs/impl_1/system_wrapper.bit
cp: cannot stat 'system_wrapper.bit.bin': No such file or directory


Please see https://github.com/parallella/oh/issues/98 for further information.
Attachments
error.txt
error log file
(30.98 KiB) Downloaded 210 times
promach
 
Posts: 6
Joined: Mon Dec 12, 2016 9:03 am

Re: FPGA Accelerator

Postby manojcs26 » Tue Sep 05, 2017 8:46 am

Even I'm facing the same issue...
I checked out the stable version and ran

Code: Select all
./build.sh


To see the same error

ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'system_i' of type 'system_i/system' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

And I noticed that the file 'system_bd.tcl' will be modified after I run build.sh.
Create Ports and Create Port Connections are gone(I assume, this is the reason for the above error).


I'm using Vivado 2015.4.

I would be really happy if someone helps me...
Im stuck with this error from almost 10 days

Thank you
manojcs26
 
Posts: 2
Joined: Thu Aug 31, 2017 6:29 am

Re: FPGA Accelerator

Postby manojcs26 » Tue Sep 05, 2017 10:43 am

I corrected the error (forgot to change the version to 2015.4 in one of the file) and got the bitstream. now I copied that bitstream to the boot directory.
Im trying to run the test present in 'accelerator/sw/'. Im compiling the test files and creating hello.elf...

Now when I try to run the executable It gives an error saying

f_map no such file exists
segmentation fault


I dont know what is the problem..
Any help would be appreciated....

Thank you
manojcs26
 
Posts: 2
Joined: Thu Aug 31, 2017 6:29 am

Re: FPGA Accelerator

Postby olajep » Tue Sep 05, 2017 3:20 pm

manojcs26 wrote:I corrected the error (forgot to change the version to 2015.4 in one of the file) and got the bitstream. now I copied that bitstream to the boot directory.
Im trying to run the test present in 'accelerator/sw/'. Im compiling the test files and creating hello.elf...

Now when I try to run the executable It gives an error saying

f_map no such file exists
segmentation fault


I dont know what is the problem..
Any help would be appreciated....

Thank you


I'm guessing the accelerator example uses an old Parabuntu image (pre 2015.1 (??)) with the old epiphany driver.

Change /dev/epiphany to /dev/mem here:
https://github.com/parallella/oh/blob/7 ... iver.c#L70
https://github.com/parallella/oh/blob// ... iver.c#L70
You need to run the program as root (e.g., use sudo) now.

Debugging segfaults 101:

Pass -ggdb -g3 to gcc
Code: Select all
$ gdb myprogram.elf
(gdb) run
Starting program: /tmp/a.out

Program received signal SIGSEGV, Segmentation fault.
0x0000000000400500 in bar () at myprogram.c:4
5       *p = 123;

(gdb) backtrace
#0  0x0000000000400500 in bar () at myprogram.c:5
#1  0x000000000040051b in quux () at myprogram.c:12
#2  0x000000000040052b in main () at myprogram.c:17

(gdb) print p
$1 = (int *) 0x0

[[so in this example it was a zero pointer dereference]]

(gdb) quit

Tyr to disable compiler optimizations if you get a nonsensical backtrace.

HTH,
Ola
_start = 266470723;
olajep
 
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Location: Sweden


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