error after make command to build a vivado project

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

error after make command to build a vivado project

Postby parallella-project » Mon May 28, 2018 5:39 am

I'm trying to build the https://github.com/olajep/parallella-fpga/tree/2016.11 project. My goal is to have a Parallella FPGA ready project in Vivado to be able for coding ans implementation on Parallella. after I cloned it, I've tried to run "make" command in the parallella-fpga folder but I get this message in the terminal:

Code: Select all
make -C AdiHDLLib/ lib
make[1]: Entering directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib'
make -C library/ all
make[2]: Entering directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib/library'
make -C axi_clkgen
make[3]: Entering directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib/library/axi_clkgen'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
vivado -mode batch -source axi_clkgen_ip.tcl  >> axi_clkgen_ip.log 2>&1
Makefile:43: recipe for target 'axi_clkgen.xpr' failed
make[3]: *** [axi_clkgen.xpr] Error 1
make[3]: Leaving directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib/library/axi_clkgen'
Makefile:96: recipe for target 'lib' failed
make[2]: [lib] Error 2 (ignored)
make -C axi_hdmi_tx
make[3]: Entering directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib/library/axi_hdmi_tx'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
vivado -mode batch -source axi_hdmi_tx_ip.tcl  >> axi_hdmi_tx_ip.log 2>&1
Makefile:55: recipe for target 'axi_hdmi_tx.xpr' failed
make[3]: *** [axi_hdmi_tx.xpr] Error 1
make[3]: Leaving directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib/library/axi_hdmi_tx'
Makefile:96: recipe for target 'lib' failed
make[2]: [lib] Error 2 (ignored)
make -C axi_spdif_tx
make[3]: Entering directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib/library/axi_spdif_tx'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
vivado -mode batch -source axi_spdif_tx_ip.tcl  >> axi_spdif_tx_ip.log 2>&1
Makefile:45: recipe for target 'axi_spdif_tx.xpr' failed
make[3]: *** [axi_spdif_tx.xpr] Error 1
make[3]: Leaving directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib/library/axi_spdif_tx'
Makefile:96: recipe for target 'lib' failed
make[2]: [lib] Error 2 (ignored)
make[2]: Leaving directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib/library'
make[1]: Leaving directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib'
make -C oh/src/parallella/fpga/parallella_base all
make[1]: Entering directory '/home/hadi/Vivado/project/parallella-fpga/oh/src/parallella/fpga/parallella_base'
vivado -mode batch -source run.tcl

****** Vivado v2015.2 (64-bit)
  **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
  **** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source run.tcl
# source ./system_params.tcl
## set design parallella_base
## set projdir ./
## set root "../../.."
## set partname "xc7z020clg400-1"
## set hdl_files [list \
##               $root/parallella/hdl \
##          $root/common/hdl/ \
##          $root/emesh/hdl \
##          $root/emmu/hdl \
##          $root/axi/hdl \
##          $root/emailbox/hdl \
##          $root/edma/hdl \
##               $root/elink/hdl \
##         ]
## set ip_files   [list \
##           $root/xilibs/ip/fifo_async_104x32.xci \
##          ]
## set constraints_files []
# source ../../../common/fpga/create_ip.tcl
## create_project -force $design $projdir -part $partname
## set_property target_language Verilog [current_project]
## set_property source_mgmt_mode None [current_project]
## if {[string equal [get_filesets -quiet sources_1] ""]} {
##     create_fileset -srcset sources_1
## }
## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
## set_property top $design [get_filesets sources_1]
## if {[string equal [get_filesets -quiet constraints_1] ""]} {
##   create_fileset -constrset constraints_1
## }
## if {[llength $constraints_files] != 0} {
##     add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files
## }
## if {[llength $ip_files] != 0} {
##     
##     #Add to fileset
##     add_files -norecurse -fileset [get_filesets sources_1] $ip_files
##
##     #Set mode for IP
##     foreach file $ip_files {
##    #TODO: is this needed?
##    set file_obj [get_files -of_objects [get_filesets sources_1] $file]
##    set_property "synth_checkpoint_mode" "Singular" $file_obj
##     }   
##     #RERUN/UPGRADE IP
##     upgrade_ip [get_ips]
## }
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.2/data/ip'.
WARNING: [Coretcl 2-1044] No upgrade is available for 'fifo_async_104x32'
WARNING: [Coretcl 2-1042] No IP was identified for upgrade.
## ipx::package_project -import_files -force -root_dir $projdir
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_mux12.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_clockor.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_ser2par.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_edgedetect.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_clockgate.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_parity.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_pll.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_crc32_64b.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_pwr_isohi.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_bin2onehot.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_mux.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_datagate.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_csa92.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_7seg_decode.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_tristate.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_iddr.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_debouncer.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_stretcher.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_mux6.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_reg1.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_edge2pulse.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_counter.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_mux8.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_csa62.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_mux5.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_delay.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_memory_sp.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_clockmux.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_crc.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_pwr_isolo.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_bitreverse.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_par2ser.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_reg0.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_8b10b_decode.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_csa42.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_mux2.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_add.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_pulse2pulse.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_pwr_gate.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_shifter.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_crc32_8b.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_lat0.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_oddr.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_standby.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_rise2pulse.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_mux7.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_clockdiv.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_8b10b_encode.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_fall2pulse.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/cfg_generic.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_lat1.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_abs.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_mux9.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_csa32.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/common/hdl/oh_pwr_buf.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/emesh/hdl/emesh_readback.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/emesh/hdl/emesh_wralign.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/emesh/hdl/emesh_constants.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/emesh/hdl/ememory.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/emesh/hdl/emesh_rdalign.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/emesh/hdl/emesh_if.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/emesh/hdl/emesh_mux.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/edma/hdl/edma_ctrl.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/edma/hdl/edma_dp.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/edma/hdl/edma.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/edma/hdl/edma_regmap.vh'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/edma/hdl/edma_regs.v'.
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '/home/hadi/Vivado/project/parallella-fpga/oh/src/elink/hdl/ecfg_if.v'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
INFO: [IP_Flow 19-2228] Inferred bus interface "m_axi" of definition type "xilinx.com:interface:aximm:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi" of definition type "xilinx.com:interface:aximm:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface "m_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface "mailbox_irq" of definition type "xilinx.com:signal:interrupt:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface "m_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0".
INFO: [IP_Flow 19-2228] Inferred bus interface "sys_clk" of definition type "xilinx.com:signal:clock:1.0".
## ipx::remove_memory_map {s_axi} [ipx::current_core]
## ipx::add_memory_map {s_axi} [ipx::current_core]
## ipx::associate_bus_interfaces -busif s_axi -clock sys_clk [ipx::current_core]
## ipx::associate_bus_interfaces -busif m_axi -clock sys_clk [ipx::current_core]
WARNING: command 'get_bus_interface' will be removed in the 2015.2 release, use 'get_bus_interfaces' instead
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]]
WARNING: command 'get_memory_map' will be removed in the 2015.2 release, use 'get_memory_maps' instead
## ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]]
WARNING: command 'get_memory_map' will be removed in the 2015.2 release, use 'get_memory_maps' instead
WARNING: command 'get_address_block' will be removed in the 2015.2 release, use 'get_address_blocks' instead
## set_property range {65536} [ipx::get_address_block axi_lite \
##     [ipx::get_memory_map s_axi [ipx::current_core]]]
## set_property vendor              {www.parallella.org}    [ipx::current_core]
## set_property library             {user}                  [ipx::current_core]
## set_property taxonomy            {{/AXI_Infrastructure}} [ipx::current_core]
## set_property vendor_display_name {ADAPTEVA}              [ipx::current_core]
## set_property company_url         {www.parallella.org}    [ipx::current_core]
## set_property supported_families  { \
##                 {virtex7}    {Production} \
##                 {qvirtex7}   {Production} \
##                 {kintex7}    {Production} \
##                 {kintex7l}   {Production} \
##                 {qkintex7}   {Production} \
##                 {qkintex7l}  {Production} \
##                 {artix7}     {Production} \
##                 {artix7l}    {Production} \
##                 {aartix7}    {Production} \
##                 {qartix7}    {Production} \
##                 {zynq}       {Production} \
##                 {qzynq}      {Production} \
##                 {azynq}      {Production} \
##                  }   [ipx::current_core]
## ipx::archive_core [concat $design.zip] [ipx::current_core]
## exit
INFO: [Common 17-206] Exiting Vivado at Sat May 26 22:29:59 2018...
make[1]: Leaving directory '/home/hadi/Vivado/project/parallella-fpga/oh/src/parallella/fpga/parallella_base'
# remove old elink simulation for now vivado -mode batch -source elinkdv.tcl
vivado -mode batch -source 7020_hdmi.tcl

****** Vivado v2015.2 (64-bit)
  **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
  **** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source 7020_hdmi.tcl
# set origin_dir "."
# set orig_proj_dir "[file normalize "$origin_dir/7020_hdmi"]"
# open_project 7020_hdmi/7020_hdmi.xpr
INFO: [Project 1-313] Project file moved from '~/parallella/parallella-fpga' since last save.
Scanning sources...
Finished scanning sources
INFO: [Project 1-230] Project '7020_hdmi.xpr' upgraded for this version of Vivado.
INFO: [Project 1-265] Setting active simulation fileset to 'sim_1'.
# set proj_dir [get_property directory [current_project]]
# set obj [get_projects 7020_hdmi]
# set_property "default_lib" "xil_defaultlib" $obj
# set_property "part" "xc7z020clg400-1" $obj
# set_property "simulator_language" "Mixed" $obj
# if {[string equal [get_filesets -quiet sources_1] ""]} {
#   create_fileset -srcset sources_1
# }
# set obj [get_filesets sources_1]
# set_property "ip_repo_paths" "[file normalize "$origin_dir/oh/src/parallella/fpga/parallella_base"] [file normalize "$origin_dir/AdiHDLLib"]" $obj
# update_ip_catalog -rebuild
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/hadi/Vivado/project/parallella-fpga/oh/src/parallella/fpga/parallella_base'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.2/data/ip'.
# set obj [get_filesets sources_1]
# set files [list \
#  "[file normalize "$orig_proj_dir/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd"]"\
#  "[file normalize "$orig_proj_dir/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v"]"\
#  "[file normalize "$orig_proj_dir/archive_project_summary.txt"]"\
# ]
# add_files -norecurse -fileset $obj $files
# set file "$orig_proj_dir/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd"
# set file [file normalize $file]
# set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
# if { ![get_property "is_locked" $file_obj] } {
#   set_property "generate_synth_checkpoint" "0" $file_obj
# }
# set_property "used_in_simulation" "0" $file_obj
# set file "$orig_proj_dir/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v"
# set file [file normalize $file]
# set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
# set_property "used_in_simulation" "0" $file_obj
# set obj [get_filesets sources_1]
# set_property "top" "elink2_top_wrapper" $obj
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
#   create_fileset -constrset constrs_1
# }
# set obj [get_filesets constrs_1]
# set file "[file normalize "$orig_proj_dir/7020_hdmi.srcs/constrs_1/imports/constraints/parallella_timing.xdc"]"
# set file_added [add_files -norecurse -fileset $obj $file]
# set file "$orig_proj_dir/7020_hdmi.srcs/constrs_1/imports/constraints/parallella_timing.xdc"
# set file [file normalize $file]
# set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
# set_property "file_type" "XDC" $file_obj
# set file "[file normalize "$orig_proj_dir/7020_hdmi.srcs/constrs_1/imports/constraints/parallella_z70x0_loc.xdc"]"
# set file_added [add_files -norecurse -fileset $obj $file]
# set file "$orig_proj_dir/7020_hdmi.srcs/constrs_1/imports/constraints/parallella_z70x0_loc.xdc"
# set file [file normalize $file]
# set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
# set_property "file_type" "XDC" $file_obj
# set file "[file normalize "$orig_proj_dir/7020_hdmi.srcs/constrs_1/imports/constraints/parallella_z7020_loc.xdc"]"
# set file_added [add_files -norecurse -fileset $obj $file]
# set file "$orig_proj_dir/7020_hdmi.srcs/constrs_1/imports/constraints/parallella_z7020_loc.xdc"
# set file [file normalize $file]
# set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
# set_property "file_type" "XDC" $file_obj
# set obj [get_filesets constrs_1]
# set_property "target_constrs_file" "$orig_proj_dir/7020_hdmi.srcs/constrs_1/imports/constraints/parallella_timing.xdc" $obj
# if {[string equal [get_filesets -quiet sim_1] ""]} {
#   create_fileset -simset sim_1
# }
# set obj [get_filesets sim_1]
# set obj [get_filesets sim_1]
# set_property "xelab.nosort" "1" $obj
WARNING: [filemgmt 56-29] Property 'xelab.nosort' is deprecated. If running in batch mode, please update your script and use 'xsim.compile.xvhdl.nosort' instead. Property 'xsim.compile.xvhdl.nosort' set to '1'.
# set_property "xelab.unifast" "" $obj
# if {[string equal [get_runs -quiet synth_1] ""]} {
#   create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
# } else {
#   set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
#   set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
# }
# set obj [get_runs synth_1]
# set_property "needs_refresh" "1" $obj
# set_property "part" "xc7z020clg400-1" $obj
# current_run -synthesis [get_runs synth_1]
# if {[string equal [get_runs -quiet impl_1] ""]} {
#   create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
# } else {
#   set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
#   set_property flow "Vivado Implementation 2014" [get_runs impl_1]
# }
# set obj [get_runs impl_1]
# set_property "needs_refresh" "1" $obj
# set_property "part" "xc7z020clg400-1" $obj
# set_property "steps.write_bitstream.args.readback_file" "0" $obj
# set_property "steps.write_bitstream.args.verbose" "0" $obj
# current_run -implementation [get_runs impl_1]
# puts "INFO: Project created:7020_hdmi"
INFO: Project created:7020_hdmi
# update_compile_order -fileset sources_1
# generate_target -quiet all [get_files $orig_proj_dir/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd]
Abnormal program termination (11)
Please check '/home/hadi/Vivado/project/parallella-fpga/hs_err_pid22965.log' for details
Makefile:7: recipe for target 'all' failed
make: *** [all] Error 139




could anyone please help me. I've stuck into this stage for a long time :( by the way, I'm using vivado 2015.2 and ubuntu 18.04

I put the hs_err_pid22965.log in here too:



Code: Select all
#
# An unexpected error has occurred (11)
#
Stack:
/lib/x86_64-linux-gnu/libc.so.6(+0x3ef20) [0x7f5a67facf20]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_coregen.so(HRSBMoDiagram::setForceValidateFlag(bool)+0) [0x7f5a57cc17c0]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_rsb.so(HRSBEnCompositeFile::_generateFor_(HSTVector<std::string, std::allocator<std::string> > const&, HDGUIStatus&, bool)+0x4a5) [0x7f5a470311a5]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_filemgmt.so(HDDACompositeFile::generateFor(HSTVector<std::string, std::allocator<std::string> > const&, HDGUIStatus&, bool)+0x494) [0x7f5a4b044cf4]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_tcltasks.so(HTCDesignGenerateTarget::execute(Tcl_Interp*)+0x8d8) [0x7f5a3a386468]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_common.so(+0x62104f) [0x7f5a690a404f]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(+0x331f5) [0x7f5a63f7f1f5]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(+0x34d6b) [0x7f5a63f80d6b]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(Tcl_EvalEx+0x16) [0x7f5a63f81276]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(Tcl_FSEvalFileEx+0x1d2) [0x7f5a63fe5d02]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_commontasks.so(+0x2f0425) [0x7f5a5f81c425]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_common.so(+0x62104f) [0x7f5a690a404f]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(+0x331f5) [0x7f5a63f7f1f5]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7f5a63f7f7e2]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7f5a63f815d2]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_commontasks.so(+0x3074a2) [0x7f5a5f8334a2]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_commontasks.so(+0x30dd9d) [0x7f5a5f839d9d]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_commontasks.so(+0x3078e3) [0x7f5a5f8338e3]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_common.so(+0x62104f) [0x7f5a690a404f]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(+0x331f5) [0x7f5a63f7f1f5]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7f5a63f7f7e2]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7f5a63f815d2]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_commonmain.so(+0x7110) [0x7f5a6887e110]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/libtcl8.5.so(Tcl_Main+0x1d5) [0x7f5a63fec175]
/opt/Xilinx/Vivado/2015.2/lib/lnx64.o/librdi_common.so(+0x659c89) [0x7f5a690dcc89]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x76db) [0x7f5a679b86db]
/lib/x86_64-linux-gnu/libc.so.6(clone+0x3f) [0x7f5a6808f88f]
parallella-project
 
Posts: 14
Joined: Sun Apr 30, 2017 5:06 pm

Re: error after make command to build a vivado project

Postby Min » Tue May 29, 2018 5:15 pm

I can build 7020_hdmi using Vivado 2015.4. But I never test the bit file. Do NOT apply patch below. I just want to show you what I modified. I tried to build the FPGA project by myself several months ago.


Code: Select all
From e65678d362191f2f88b5c145eb072cce4eefad19 Mon Sep 17 00:00:00 2001
From: minxu <xuminready@gmail.com>
Date: Tue, 29 May 2018 10:02:25 -0700
Subject: [PATCH] 7020

---
 7010_hdmi/7010_hdmi.xpr                            | 29 ++--------------------
 .../sources_1/bd/elink2_top/elink2_top.bd          |  2 +-
 .../bd/elink2_top/hdl/elink2_top_wrapper.v         |  4 +--
 7020_hdmi/7020_hdmi.xpr                            |  2 +-
 Makefile                                           |  4 +--
 oh                                                 |  2 +-
 6 files changed, 9 insertions(+), 34 deletions(-)

diff --git a/7010_hdmi/7010_hdmi.xpr b/7010_hdmi/7010_hdmi.xpr
index a12921d..105ecf8 100644
--- a/7010_hdmi/7010_hdmi.xpr
+++ b/7010_hdmi/7010_hdmi.xpr
@@ -3,7 +3,7 @@
 <!--                                                         -->
 <!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.   -->
 
-<Project Version="7" Minor="10" Path="/opt/olaj/src/parallella-fpga/7010_hdmi/7010_hdmi.xpr">
+<Project Version="7" Minor="10" Path="/home/minxu/Desktop/parallella-fpga/7010_hdmi/7010_hdmi.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="142e386e71f248369dcfc3a475c449a1"/>
@@ -34,30 +34,6 @@
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
         </FileInfo>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_axi_interconnect_2_0/elink2_top_axi_interconnect_2_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_axi_interconnect_1_0/elink2_top_axi_interconnect_1_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_parallella_base_0_0/elink2_top_parallella_base_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_processing_system7_0_0_1/elink2_top_processing_system7_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_proc_sys_reset_0_0_1/elink2_top_proc_sys_reset_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_xlconcat_0_0/elink2_top_xlconcat_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_axi_interconnect_0_0/elink2_top_axi_interconnect_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_xlconstant_0_0/elink2_top_xlconstant_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="hdl/elink2_top.v"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_clk_wiz_0_0/elink2_top_clk_wiz_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_axi_interconnect_0_1/elink2_top_axi_interconnect_0_1.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_axi_vdma_0_0/elink2_top_axi_vdma_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_axi_spdif_tx_0_0/elink2_top_axi_spdif_tx_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_axi_hdmi_tx_0_0/elink2_top_axi_hdmi_tx_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_axi_clkgen_0_0/elink2_top_axi_clkgen_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_xbar_0/elink2_top_xbar_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_auto_pc_2/elink2_top_auto_pc_2.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_auto_pc_1/elink2_top_auto_pc_1.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="hw_handoff/elink2_top_bd.tcl"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="hw_handoff/elink2_top.hwh"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="hdl/elink2_top.hwdef"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="elink2_top_ooc.xdc"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_auto_pc_0/elink2_top_auto_pc_0.xci"/>
-        <CompFileExtendedInfo CompFileName="elink2_top.bd" FileRelPathName="ip/elink2_top_auto_pc_3/elink2_top_auto_pc_3.xci"/>
       </File>
       <File Path="$PSRCDIR/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v">
         <FileInfo>
@@ -131,7 +107,7 @@
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
         <Step Id="init_design"/>
@@ -144,7 +120,6 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
     </Run>
   </Runs>
 </Project>
diff --git a/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd b/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd
index 4098831..ec6ddc8 100644
--- a/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd
+++ b/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd
@@ -2371,7 +2371,7 @@
         <spirit:instanceName>xbar</spirit:instanceName>
         <spirit:componentRef spirit:library="ip" spirit:name="axi_crossbar" spirit:vendor="xilinx.com" spirit:version="2.1"/>
         <spirit:configurableElementValues>
-          <spirit:configurableElementValue spirit:referenceId="bd:xciName">elink2_top_xbar_1</spirit:configurableElementValue>
+          <spirit:configurableElementValue spirit:referenceId="bd:xciName">elink2_top_xbar_0</spirit:configurableElementValue>
           <spirit:configurableElementValue spirit:referenceId="NUM_SI">1</spirit:configurableElementValue>
           <spirit:configurableElementValue spirit:referenceId="NUM_MI">4</spirit:configurableElementValue>
           <spirit:configurableElementValue spirit:referenceId="STRATEGY">0</spirit:configurableElementValue>
diff --git a/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v b/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v
index db7c1e4..442fd77 100644
--- a/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v
+++ b/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v
@@ -1,8 +1,8 @@
 //Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
 //--------------------------------------------------------------------------------
 //Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-//Date        : Fri Dec  2 13:34:00 2016
-//Host        : ola-laptop running 64-bit Fedora release 20 (Heisenbug)
+//Date        : Mon Mar 12 10:08:18 2018
+//Host        : minxu-VirtualBox running 64-bit Ubuntu 17.10
 //Command     : generate_target elink2_top_wrapper.bd
 //Design      : elink2_top_wrapper
 //Purpose     : IP block netlist
diff --git a/7020_hdmi/7020_hdmi.xpr b/7020_hdmi/7020_hdmi.xpr
index 0941328..9bcffea 100644
--- a/7020_hdmi/7020_hdmi.xpr
+++ b/7020_hdmi/7020_hdmi.xpr
@@ -3,7 +3,7 @@
 <!--                                                         -->
 <!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.   -->
 
-<Project Version="7" Minor="10" Path="/opt/olaj/src/parallella-fpga/7020_hdmi/7020_hdmi.xpr">
+<Project Version="7" Minor="10" Path="/home/minxu/Desktop/parallella-fpga/7020_hdmi/7020_hdmi.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="dad3b4fd441447bb9d7154ec7cfdb34f"/>
diff --git a/Makefile b/Makefile
index 7df9e3c..1df69d6 100644
--- a/Makefile
+++ b/Makefile
@@ -15,8 +15,8 @@ all: $(ADI_IPS)
    # remove old elink simulation for now $(M_VIVADO) elinkdv.tcl
    $(M_VIVADO) 7020_hdmi.tcl
    cd 7020_hdmi ; rm -f bit2bin.bin elink2_top_wrapper.bit.bin ; bootgen -image bit2bin.bif -split bin ; cd ..
-   $(M_VIVADO) 7010_hdmi.tcl
-   cd 7010_hdmi ; rm -f bit2bin.bin elink2_top_wrapper.bit.bin ; bootgen -image bit2bin.bif -split bin ; cd ..
+   #$(M_VIVADO) 7010_hdmi.tcl
+   #cd 7010_hdmi ; rm -f bit2bin.bin elink2_top_wrapper.bit.bin ; bootgen -image bit2bin.bif -split bin ; cd ..
 
 $(ADI_IPS):
    make -C AdiHDLLib/library/$@
diff --git a/oh b/oh
index 17d11ce..998f302 160000
--- a/oh
+++ b/oh
@@ -1 +1 @@
-Subproject commit 17d11ce13c4a27101b993ad01dbb0fe27614d2ba
+Subproject commit 998f3021cced74e584b829ede8c566e8088c3587
--
2.14.1
Min
 
Posts: 11
Joined: Fri Feb 23, 2018 6:03 am

Re: error after make command to build a vivado project

Postby parallella-project » Tue May 29, 2018 6:16 pm

Hi,
Could you just tell me step by step what have you done exactly?
I just want to create a new project by this repository to be able to code in Vivado (PL and PS and epiphany). I'm not very familiar with scripts or Linux for now! :roll:
I've tried a lot of method to build so far but there is no progress :|
parallella-project
 
Posts: 14
Joined: Sun Apr 30, 2017 5:06 pm

Re: error after make command to build a vivado project

Postby Min » Fri Jun 01, 2018 11:55 pm

I notice you use Vivado 2015.2.
/opt/Xilinx/Vivado/2015.2

Try to use Vivado 2015.4. I can build 7020_hdmi without any problem today.
Min
 
Posts: 11
Joined: Fri Feb 23, 2018 6:03 am

Re: error after make command to build a vivado project

Postby parallella-project » Sat Jun 02, 2018 8:15 am

I also used 2015.4 but at the end some errors were occurred (these are some of the last errors that appear in the terminal):

Code: Select all
Adding component instance block -- analog.com:user:axi_clkgen:1.0 - axi_clkgen_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: elink2_top_axi_clkgen_0_0
ERROR: [BD 41-50] Could not find an IP with the given vlnv: analog.com:user:axi_clkgen:1.0
ERROR: [BD 41-595] Failed to add ip repository block <axi_clkgen_0>
ERROR: [BD 41-425] Failed to read Diagram <elink2_top> from BD file </home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd>
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding component instance block -- www.parallella.org:user:parallella_base:1.0 - parallella_base_0
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- analog.com:user:axi_clkgen:1.0 - axi_clkgen_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: elink2_top_axi_clkgen_0_0
ERROR: [BD 41-50] Could not find an IP with the given vlnv: analog.com:user:axi_clkgen:1.0
ERROR: [BD 41-595] Failed to add ip repository block <axi_clkgen_0>
ERROR: [BD 41-425] Failed to read Diagram <elink2_top> from BD file </home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd>
WARNING: [Runs 36-53] Possible issues detected after target generation. Generation state is unexpected for target 'Synthesis'. Expected 'Generated', got 'Stale' for source '/home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd'
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding component instance block -- www.parallella.org:user:parallella_base:1.0 - parallella_base_0
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- analog.com:user:axi_clkgen:1.0 - axi_clkgen_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: elink2_top_axi_clkgen_0_0
ERROR: [BD 41-50] Could not find an IP with the given vlnv: analog.com:user:axi_clkgen:1.0
ERROR: [BD 41-595] Failed to add ip repository block <axi_clkgen_0>
ERROR: [BD 41-425] Failed to read Diagram <elink2_top> from BD file </home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd>
WARNING: [Runs 36-53] Possible issues detected after target generation. Generation state is unexpected for target 'Implementation'. Expected 'Generated', got 'Stale' for source '/home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd'
[Sat Jun  2 12:40:16 2018] Launched synth_1...
Run output will be captured here: /home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.runs/synth_1/runme.log
ERROR: [Common 17-39] 'launch_runs' failed due to earlier errors.

    while executing
"launch_runs synth_1"
    (file "7020_hdmi.tcl" line 180)
INFO: [Common 17-206] Exiting Vivado at Sat Jun  2 12:40:16 2018...
Makefile:7: recipe for target 'all' failed
make: *** [all] Error 1
Last edited by parallella-project on Mon Jun 04, 2018 10:16 am, edited 1 time in total.
parallella-project
 
Posts: 14
Joined: Sun Apr 30, 2017 5:06 pm

Re: error after make command to build a vivado project

Postby parallella-project » Sat Jun 02, 2018 8:19 am

these are in the runme.log:


Code: Select all
*** Running vivado
    with args -log elink2_top_wrapper.vds -m64 -mode batch -messageDb vivado.pb -notrace -source elink2_top_wrapper.tcl


****** Vivado v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source elink2_top_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/oh/src/parallella/fpga/parallella_base'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/AdiHDLLib'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx.15.4/Vivado/2015.4/data/ip'.
Command: synth_design -top elink2_top_wrapper -part xc7z020clg400-1 -verilog_define CFG_ASIC=0
Starting synth_design
WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd

WARNING: [Vivado_Tcl 4-393] The 'Implementation' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd

Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1078.074 ; gain = 225.160 ; free physical = 339 ; free virtual = 7429
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'elink2_top_wrapper' [/home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v:12]
ERROR: [Synth 8-439] module 'elink2_top' not found [/home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v:180]
ERROR: [Synth 8-285] failed synthesizing module 'elink2_top_wrapper' [/home/hadi/Vivado/project/peatsa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v:12]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1116.449 ; gain = 263.535 ; free physical = 300 ; free virtual = 7390
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
7 Infos, 2 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Sat Jun  2 12:40:30 2018...
parallella-project
 
Posts: 14
Joined: Sun Apr 30, 2017 5:06 pm

Re: error after make command to build a vivado project

Postby Min » Tue Jun 05, 2018 5:18 pm

I use this repo: https://github.com/parallella/parallella-fpga.git
And here's my command history to build the project.

Code: Select all
git clone https://github.com/parallella/parallella-fpga.git --depth=1

cd parallella-fpga/

git submodule init
git submodule update

source /opt/Xilinx/Vivado/2015.4/settings64.sh
make
Min
 
Posts: 11
Joined: Fri Feb 23, 2018 6:03 am


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