is it correct that the SYNC interrupt on the core is like everything else in the IVT with the exception that it's the only interrupt that can be called when the core is idle?
what happens when one send and IRQ that isnt SYNC to an idle core?
can memory be read or written from another core while that other core is in the middle of using that memory? (it's bad idea but i gotta know!)
if so, does it vary between instructions due to the variable length pipeline and what stage of the pipeline would the reading/writing happen?
i'm hoping you can provide a code snippet (assembly) of...
- writing to memory on another core
- reading memory from another core
- executing an IRQ on another core
i get the feeling memory and IRQ execution are done in the same manner but i want to be sure.
if you didnt guess, i'm working on the DMA engine and DMA handling for my emulator.
