I presume (hope!) this is merely just a "we''re working on it" question, but here goes anyway.
From the examples (and e-hal), there seems to be no way for the ARM to "wait" for epiphany cores to complete without either sleeping "in hope", or presumably a busy wait reading an absolute location. A quick glance through the e-hal code seems to suggest there isn't a device driver as such and the whole chip is just controlled using memory mapped i/o.
I guess my question is: will the epiphany cores eventually be able to raise interrupts on the host device, and have it exposed one way or another via e-hal. i.e. at least a non-busy 'wait', but I guess the FPGA allows for all sorts of possibilities - from a simple interrupt bit to (bi-directional) a hardware mailbox, etc.
I presume the FPGA logic has access to raising interrupts and like other ARM SOCs i've looked at the zynq has a pile available.
Or is this just something which for now will be open for us users to experiment with?
I searched through the forums but all I saw was talk about e-core to e-core communications.