Parallella Community

is there any plan for 64/128 bit addressing in future chips?

I'm not part of Adapteva, but if you look at their roadmap at the bottom of , you will notice a chip with 64K cores each with 1MB memory. By my reckoning that needs more than 32 address bits, just for the single chip.

I've no idea how easy it will be to get that volume of data in and out in a timely manner. (The E64 does 6.4 GB per second peak over all four links at once.) Perhaps best where a lot of computation takes place on the initial data, e.g. weather prediction.

Tim

@Tim I don't know what to say but if adapteva wants to use thir power they have to find a way to address more than 4GB.
I know that GPU-s very recently (1-2 years) have crossed this barrier in main stream but still.
At least it makes writing sw easy if you don't have to care where data is located.
the data flow programming is catching up but is not really wide used.
with that you could probably go away even with 16 bit cause you just go through the flow.

@Gravis: these are stone age techniques. These were used in the times before 80486...

There are a couple more problems related to memory expansion via the FPGA.

* first and foremost, the elink bandwidth into the FPGA is limited - a fraction of present-day RAM bandwidth
* secondly, that limited B/W is shared by 16 cores
* then, there is no cache to insulate the cores from the performance hit of accessing that RAM

Sure bank-switching allows more RAM to be present in the system than can be addressed (and in fact even with Epiphany-III it is possible to have more than 4GB of total RAM in the system*), but then the programmer and/or compiler must be bank aware - and this too has a performance penalty, even with the approx 1uS cycle time and 0.1MFlop of an HP2117F). Virtual memory gives the system the illusion that there is more RAM than is actually present, which is even worse for performance because a page fault has a penalty of hundreds of microseconds - and in a parallel system will cause a processing "bubble" that cause all the other cores to sit picking their teeth at the next global synchronisation point.

* the one glimmer of hope is an artifact of the mesh transaction routing - with east-west being the first routing direction, any accesses to memory with an external e-mesh column address will exit via the East or West end of that row. So if the e-mesh rows are half-populated with Epiphany-III chips (i.e. 32 cores per row) as much as 64 x 32 x 1MB = 2GB of external RAM can be attached to each row. There is of course the problem that this address space is both aliased and non-contiguous, but I guess one can't have everything. NB even with this arrangement, the performance differential is such that external RAM is best viewed as secondary storage.

Edit: a few months I had a madly optimistic idea to interpose an FPGA between each pair of Epiphanies thus quadrupling the external RAM bandwidth per Epiphany and greatly increasing the total address space due to the above aliasing effect. Once the coffe-buzz had worn off it became clear that the cost and heat would negate the advantages of the Epiphany architecture, never mind the challenge of writing intelligible software for such a mad scheme...

Mark

@Mark: I couldn't have explained it better.

Even so Mark what is your opinion in making a laptop out adapteva chips. Lets say you have like a plate with adapteva chips in the middle and on the borders ARM chips connected to RAM. These would communicate through this mesh and establish processing pathways which would be reconfigured on the fly depending on the computing needs.

Would this work?

[Usual disclaimer: I'm a software engineer with a fascination for system architecture!]

Sadly I don't think so... for a general purpose computer - especially with today's operating systems - for a responsive user interface it is necessary to have very good single-threaded performance (plus a spare core so that the OS housekeeping tasks don't get in the way).

The RAM size and bandwidth constraints of the present Epiphany product severely limit the range of applications for which it is useful. So despite the heat issues, for laptop use the x86 + GPU-accelerator model looks most attractive. This is because the GPU is multi-purpose - better graphics rendering increases the system responsiveness, and the GPU can assist with typical "portable workstation" applications.

That said, I did have a coffee-fuelled moment in which the vision of a multi-Epiphany board conforming to the format and interface of a laptop optical drive popped into my head. But then I couldn't think of anyone who would buy such a beast, and the reality of the RAM limitations came and ensured total deflation...

hmmm.... I have to recognize you might be right...