Parallella Community

@Gravis: I think you are confusing virtual memory with memory addressing.
virtual memory is so that several processes may access the same amount of memory as if the run alone on a hardware. Memory addressing/pagination and so on is used to allow a system that has an addressing space of lets say 4GB access 16GB. For the process it looks as if it is running in a 64 bit environment yet the physical addressing is only 32bit. The OS or the hardware or a combination kicks in and swaps the backs accessed at any one time so that it gives the program the illusion it has a bigger memory space.
While the first one helps mitigate the running in parallel of several processes the second one mitigates the need for more memory of a single process.
If parallela chips would have in hardware implemented 64 or 128 bit addressing the software would not have to do all these tricks which are pretty tedious and taxing in terms of computing power. Yes they can be done in SW but there is no need.
here we can talk about bandwidth. If you have a 64 bit or 128 bit bus to send the addresses there is the problem of heat plus the hardware is more complicated. but one may use a serial bus and probably the guys from rambus will come knocking on the door for fees.
On this serial bus you can use near or far or huge addressing sending only the amount of bytes necessary and by this reducing the required bandwidth and saving some energy.
Anyhow... I think implementing a memory access in hardware that allows one to use large amounts of RAM is a must for a chip like parallela if it is to compete with heavy weights like knight corner tegra k1 or other mammoths...