Parallella Community

Do we know what Adapteva's position would be on a clean room rewrite? I don't think anyone is looking to upset them.

There are two matters that immediately come to mind

Adapteva have not as far as I know published any details such as timing diagrams for the eLink. The timing diagrams in the chip manuals are for using the FPGA HDL to talk to the eLink, not for the raw eLink.

Do Adapteva feel they have patents that would cover a clean room implementation? Under the GPL they have granted a royalty free license for any patents that there might be. If you don't use the GPL, you don't have that particular grant.

Tim

It might be a good idea to contact Adapteva directly about this. I'm not sure how this FPGA programming stuff works, but if you don't actually reference the adapteva stuff anywhere - That is, if the only connection between your stuff and adapteva's stuff is that they must somehow arrange themselves on the same FPGA - Then I think it'd be in the best interest of everyone involved to not count this as "derivative".

@CIB: If you used somehow used partial configuration to load both part independently and they shared no connectivity that might be defendable, but if you ship a single .bit file, no cigar, the whole bitstream is definitely derivative (it includes all the adapteva stuff ...) and so it's whole source must be available.