A few questions

Any technical questions about the Epiphany chip and Parallella HW Platform.

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A few questions

Postby Mukti » Tue Jul 30, 2013 9:49 am

Can Parallella run Apache web server ?
Can Parallella run Tomcat server ?
Can the Eclipse IDE on Parallella compile and/or execute Java ?
Will there be a box/container/rack for Parallella blades available for sale ?
Can we still donate funds for research on Parallella-64 ?
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Re: A few questions

Postby 9600 » Tue Jul 30, 2013 12:10 pm

Hi Mukti,

Mukti wrote:Can Parallella run Apache web server ?


Yes.

Mukti wrote:Can Parallella run Tomcat server ?


Yes.

Mukti wrote:Can the Eclipse IDE on Parallella compile and/or execute Java ?


The Eclipse IDE that ships with the Epiphany SDK is meant for use in developing C/C++ applications that use the Epiphany accelerator.

Given the Java related questions I should point out that, at present, if you run Tomcat/Java apps on Parallella you will only be making use of the dual-core ARM in the Zynq SoC. Someone is looking at extending the OpenJDK JVM such that certain operations can be offloaded to the Epiphany accelerator, but it is early days. Of course, if you have JVM experience this would be an excellent and worthwhile project to contribute to!

Mukti wrote:Will there be a box/container/rack for Parallella blades available for sale ?


If by "blades" you mean the Parallella board then, yes, enclosures are planned, but I'm not aware of a rack solution on the cards just yet.

Mukti wrote:Can we still donate funds for research on Parallella-64 ?


As far as I am aware no research is required, and 64-core Epiphany engineering samples have been produced and Parallella-64 boards will go out to a limited number of backers.

However, further engineering work is required in order to take the 64-core Epiphany IV into volume production. The original Kickstarter campaign finished last year and the stretch goal wasn't met. The priority now is to deliver on the commitment made to backers. After which, who knows... :)

Cheers,

Andrew
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Re: A few questions

Postby Mukti » Tue Jul 30, 2013 4:50 pm

Thanks for the prompt response.

I have some more questions:

Does each Parallella board in a stack have/need it's own OS ?
Does 4x Parallella boards mean 4x 1GB RAM (Does Parallella use distributed memory or Memory virtualization) ?
When will the enclosure pre-orders be available ?
What is the timeframe for Parallella-64 pre-orders ?
Last edited by Mukti on Tue Jul 30, 2013 5:00 pm, edited 1 time in total.
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Re: A few questions

Postby 9600 » Tue Jul 30, 2013 4:58 pm

Mukti wrote:Does each Parallella board in a stack have/need it's own OS ?


Yes.

Mukti wrote:Does 4x Parallella boards mean 4x 1GB RAM (will a Application's load on the Memory also be distributed) ?


Yes, you will have 4 x 1GB RAM, and it would be up to your application to manage this.

Mukti wrote:When will Parallella-64 pre-orders be available ?


Q4 2013.

Mukti wrote:When will the enclosure pre-orders be available ?


I'm not sure. Perhaps Andreas or Yaniv could comment.

Cheers,

Andrew
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Re: A few questions

Postby Mukti » Tue Jul 30, 2013 5:01 pm

Wow THAT was FAST !
Thanks :)
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Re: A few questions

Postby Mukti » Wed Mar 05, 2014 10:48 am

So how much progress has been made on Parallella-64 ?
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Re: A few questions

Postby 9600 » Wed Mar 05, 2014 3:52 pm

Mukti wrote:So how much progress has been made on Parallella-64 ?


There is very little difference between the 16 and 64-core boards in terms of their design and it's mainly the generation of Epiphany silicon that is fitted — which obviously dictates the number of cores.

Some backers who pledged higher amounts will be receiving boards with E64 chips. However, the stretch goal wasn't met so as far as I know there hasn't been the extra work done to increase the yield of the 64-core silicon and to bring the cost down.

Cheers,

Andrew
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Re: A few questions

Postby mxfreak » Thu Mar 13, 2014 2:08 pm

Hello,

I have another question:

Written in the article about the network topology: "Transactions move through the network, with a latency of 1.5 clock cycles per hop. A transaction traversing from the left edge to right edge of 64-core chip would thus take 12 clock cycles."

Am I right that this message implies that the network operates on rising-edge AND falling-edge? Like a DDR-RAM?
Otherwise i can't explain to myself the half clock cycle?!

Kind regards,
mx
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Re: A few questions

Postby timpart » Thu Mar 13, 2014 5:50 pm

mxfreak wrote:Written in the article about the network topology: "Transactions move through the network, with a latency of 1.5 clock cycles per hop. A transaction traversing from the left edge to right edge of 64-core chip would thus take 12 clock cycles."

Am I right that this message implies that the network operates on rising-edge AND falling-edge? Like a DDR-RAM?
Otherwise i can't explain to myself the half clock cycle?!
mx


Andreas explained it here, under buffering. This trick seems to reduce the delay from two cycles to 1.5. See the next post too for a link to the patent with diagrams.

Tim
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Re: A few questions

Postby mxfreak » Sat Mar 15, 2014 1:25 pm

Thanks a lot!
This link was really helpful :)
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